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authorAndrew Kannan <andrew.kannan@klaviyo.com>2019-09-16 22:37:51 -0400
committerMechMerlin <30334081+mechmerlin@users.noreply.github.com>2019-09-16 19:37:51 -0700
commit59af2cbe640191345175bf34fd65f78ab1036647 (patch)
tree52fa752e63ca9f7c3056ac78cfbaf8cdd12f328f
parent7c1bb9decf00a19cdf85ab33830dcc9002bfc671 (diff)
downloadqmk_firmware-59af2cbe640191345175bf34fd65f78ab1036647.tar.gz
qmk_firmware-59af2cbe640191345175bf34fd65f78ab1036647.zip
Add Chimera65 Keyboard (#6670)
* Add chimera board * info json start * Update keyboards/cannonkeys/chimera65/config.h Co-Authored-By: Drashna Jaelre <drashna@live.com> * Apply suggestions from code review Co-Authored-By: Drashna Jaelre <drashna@live.com> Co-Authored-By: noroadsleft <18669334+noroadsleft@users.noreply.github.com> * Update keyboards/cannonkeys/chimera65/config.h Co-Authored-By: Drashna Jaelre <drashna@live.com>
Diffstat
-rw-r--r--keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.c109
-rw-r--r--keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.h922
-rw-r--r--keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.mk5
-rw-r--r--keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg703
-rw-r--r--keyboards/cannonkeys/chimera65/bootloader_defs.h7
-rw-r--r--keyboards/cannonkeys/chimera65/chconf.h524
-rw-r--r--keyboards/cannonkeys/chimera65/chimera65.c1
-rw-r--r--keyboards/cannonkeys/chimera65/chimera65.h17
-rw-r--r--keyboards/cannonkeys/chimera65/config.h89
-rw-r--r--keyboards/cannonkeys/chimera65/halconf.h354
-rw-r--r--keyboards/cannonkeys/chimera65/info.json7
-rw-r--r--keyboards/cannonkeys/chimera65/keymaps/default/keymap.c44
-rw-r--r--keyboards/cannonkeys/chimera65/keymaps/via/keymap.c44
-rw-r--r--keyboards/cannonkeys/chimera65/keymaps/via/rules.mk5
-rw-r--r--keyboards/cannonkeys/chimera65/mcuconf.h176
-rw-r--r--keyboards/cannonkeys/chimera65/readme.md12
-rw-r--r--keyboards/cannonkeys/chimera65/rules.mk57
-rw-r--r--keyboards/cannonkeys/stm32f072/keyboard.c3
18 files changed, 3077 insertions, 2 deletions
diff --git a/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.c b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.c
new file mode 100644
index 000000000..9d10fbd75
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.c
@@ -0,0 +1,109 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#include "hal.h"
23
24#if HAL_USE_PAL || defined(__DOXYGEN__)
25/**
26 * @brief PAL setup.
27 * @details Digital I/O ports static configuration as defined in @p board.h.
28 * This variable is used by the HAL when initializing the PAL driver.
29 */
30const PALConfig pal_default_config = {
31#if STM32_HAS_GPIOA
32 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
33 VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
34#endif
35#if STM32_HAS_GPIOB
36 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
37 VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
38#endif
39#if STM32_HAS_GPIOC
40 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
41 VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
42#endif
43#if STM32_HAS_GPIOD
44 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
45 VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
46#endif
47#if STM32_HAS_GPIOE
48 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
49 VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
50#endif
51#if STM32_HAS_GPIOF
52 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
53 VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
54#endif
55#if STM32_HAS_GPIOG
56 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
57 VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
58#endif
59#if STM32_HAS_GPIOH
60 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
61 VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
62#endif
63#if STM32_HAS_GPIOI
64 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
65 VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
66#endif
67};
68#endif
69
70void enter_bootloader_mode_if_requested(void);
71
72/**
73 * @brief Early initialization code.
74 * @details This initialization must be performed just after stack setup
75 * and before any other initialization.
76 */
77void __early_init(void) {
78 enter_bootloader_mode_if_requested();
79 stm32_clock_init();
80}
81
82#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
83/**
84 * @brief MMC_SPI card detection.
85 */
86bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
87
88 (void)mmcp;
89 /* TODO: Fill the implementation.*/
90 return true;
91}
92
93/**
94 * @brief MMC_SPI card write protection detection.
95 */
96bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
97
98 (void)mmcp;
99 /* TODO: Fill the implementation.*/
100 return false;
101}
102#endif
103
104/**
105 * @brief Board-specific initialization code.
106 * @todo Add your board-specific code, if any.
107 */
108void boardInit(void) {
109}
diff --git a/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.h b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.h
new file mode 100644
index 000000000..de3a93d1c
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.h
@@ -0,0 +1,922 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#ifndef BOARD_H
23#define BOARD_H
24
25/*
26 * Setup for ST STM32F072B-Discovery board.
27 */
28
29/*
30 * Board identifier.
31 */
32#define BOARD_ST_STM32F072B_DISCOVERY
33#define BOARD_NAME "ST STM32F072B-Discovery"
34
35/*
36 * Board oscillators-related settings.
37 * NOTE: HSE not fitted.
38 */
39#if !defined(STM32_LSECLK)
40#define STM32_LSECLK 32768
41#endif
42
43#define STM32_LSEDRV (3U << 3U)
44
45#if !defined(STM32_HSECLK)
46#define STM32_HSECLK 0U
47#endif
48
49#define STM32_HSE_BYPASS
50
51/*
52 * MCU type as defined in the ST header.
53 */
54#define STM32F072xB
55
56/*
57 * IO pins assignments.
58 */
59#define GPIOA_BUTTON 0U
60#define GPIOA_PIN1 1U
61#define GPIOA_PIN2 2U
62#define GPIOA_PIN3 3U
63#define GPIOA_PIN4 4U
64#define GPIOA_PIN5 5U
65#define GPIOA_PIN6 6U
66#define GPIOA_PIN7 7U
67#define GPIOA_PIN8 8U
68#define GPIOA_PIN9 9U
69#define GPIOA_PIN10 10U
70#define GPIOA_USB_DM 11U
71#define GPIOA_USB_DP 12U
72#define GPIOA_SWDIO 13U
73#define GPIOA_SWCLK 14U
74#define GPIOA_PIN15 15U
75
76#define GPIOB_PIN0 0U
77#define GPIOB_PIN1 1U
78#define GPIOB_PIN2 2U
79#define GPIOB_PIN3 3U
80#define GPIOB_PIN4 4U
81#define GPIOB_PIN5 5U
82#define GPIOB_PIN6 6U
83#define GPIOB_PIN7 7U
84#define GPIOB_PIN8 8U
85#define GPIOB_PIN9 9U
86#define GPIOB_PIN10 10U
87#define GPIOB_PIN11 11U
88#define GPIOB_PIN12 12U
89#define GPIOB_SPI2_SCK 13U
90#define GPIOB_SPI2_MISO 14U
91#define GPIOB_SPI2_MOSI 15U
92
93#define GPIOC_MEMS_CS 0U
94#define GPIOC_PIN1 1U
95#define GPIOC_PIN2 2U
96#define GPIOC_PIN3 3U
97#define GPIOC_PIN4 4U
98#define GPIOC_PIN5 5U
99#define GPIOC_LED_RED 6U
100#define GPIOC_LED_BLUE 7U
101#define GPIOC_LED_ORANGE 8U
102#define GPIOC_LED_GREEN 9U
103#define GPIOC_PIN10 10U
104#define GPIOC_PIN11 11U
105#define GPIOC_PIN12 12U
106#define GPIOC_PIN13 13U
107#define GPIOC_OSC32_IN 14U
108#define GPIOC_OSC32_OUT 15U
109
110#define GPIOD_PIN0 0U
111#define GPIOD_PIN1 1U
112#define GPIOD_PIN2 2U
113#define GPIOD_PIN3 3U
114#define GPIOD_PIN4 4U
115#define GPIOD_PIN5 5U
116#define GPIOD_PIN6 6U
117#define GPIOD_PIN7 7U
118#define GPIOD_PIN8 8U
119#define GPIOD_PIN9 9U
120#define GPIOD_PIN10 10U
121#define GPIOD_PIN11 11U
122#define GPIOD_PIN12 12U
123#define GPIOD_PIN13 13U
124#define GPIOD_PIN14 14U
125#define GPIOD_PIN15 15U
126
127#define GPIOE_PIN0 0U
128#define GPIOE_PIN1 1U
129#define GPIOE_PIN2 2U
130#define GPIOE_PIN3 3U
131#define GPIOE_PIN4 4U
132#define GPIOE_PIN5 5U
133#define GPIOE_PIN6 6U
134#define GPIOE_PIN7 7U
135#define GPIOE_PIN8 8U
136#define GPIOE_PIN9 9U
137#define GPIOE_PIN10 10U
138#define GPIOE_PIN11 11U
139#define GPIOE_PIN12 12U
140#define GPIOE_PIN13 13U
141#define GPIOE_PIN14 14U
142#define GPIOE_PIN15 15U
143
144#define GPIOF_OSC_IN 0U
145#define GPIOF_OSC_OUT 1U
146#define GPIOF_PIN2 2U
147#define GPIOF_PIN3 3U
148#define GPIOF_PIN4 4U
149#define GPIOF_PIN5 5U
150#define GPIOF_PIN6 6U
151#define GPIOF_PIN7 7U
152#define GPIOF_PIN8 8U
153#define GPIOF_PIN9 9U
154#define GPIOF_PIN10 10U
155#define GPIOF_PIN11 11U
156#define GPIOF_PIN12 12U
157#define GPIOF_PIN13 13U
158#define GPIOF_PIN14 14U
159#define GPIOF_PIN15 15U
160
161/*
162 * IO lines assignments.
163 */
164#define LINE_BUTTON PAL_LINE(GPIOA, 0U)
165#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
166#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
167#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
168#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
169
170#define LINE_SPI2_SCK PAL_LINE(GPIOB, 13U)
171#define LINE_SPI2_MISO PAL_LINE(GPIOB, 14U)
172#define LINE_SPI2_MOSI PAL_LINE(GPIOB, 15U)
173
174#define LINE_MEMS_CS PAL_LINE(GPIOC, 0U)
175#define LINE_LED_RED PAL_LINE(GPIOC, 6U)
176#define LINE_LED_BLUE PAL_LINE(GPIOC, 7U)
177#define LINE_LED_ORANGE PAL_LINE(GPIOC, 8U)
178#define LINE_LED_GREEN PAL_LINE(GPIOC, 9U)
179#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
180#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
181
182
183
184#define LINE_OSC_IN PAL_LINE(GPIOF, 0U)
185#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U)
186
187/*
188 * I/O ports initial setup, this configuration is established soon after reset
189 * in the initialization code.
190 * Please refer to the STM32 Reference Manual for details.
191 */
192#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
193#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
194#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
195#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
196#define PIN_ODR_LOW(n) (0U << (n))
197#define PIN_ODR_HIGH(n) (1U << (n))
198#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
199#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
200#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
201#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
202#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
203#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
204#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
205#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
206#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
207#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
208
209/*
210 * GPIOA setup:
211 *
212 * PA0 - BUTTON (input floating).
213 * PA1 - PIN1 (input pullup).
214 * PA2 - PIN2 (input pullup).
215 * PA3 - PIN3 (input pullup).
216 * PA4 - PIN4 (input pullup).
217 * PA5 - PIN5 (input pullup).
218 * PA6 - PIN6 (input pullup).
219 * PA7 - PIN7 (input pullup).
220 * PA8 - PIN8 (input pullup).
221 * PA9 - PIN9 (input pullup).
222 * PA10 - PIN10 (input pullup).
223 * PA11 - USB_DM (input floating).
224 * PA12 - USB_DP (input floating).
225 * PA13 - SWDIO (alternate 0).
226 * PA14 - SWCLK (alternate 0).
227 * PA15 - PIN15 (input pullup).
228 */
229#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
230 PIN_MODE_INPUT(GPIOA_PIN1) | \
231 PIN_MODE_INPUT(GPIOA_PIN2) | \
232 PIN_MODE_INPUT(GPIOA_PIN3) | \
233 PIN_MODE_INPUT(GPIOA_PIN4) | \
234 PIN_MODE_INPUT(GPIOA_PIN5) | \
235 PIN_MODE_INPUT(GPIOA_PIN6) | \
236 PIN_MODE_INPUT(GPIOA_PIN7) | \
237 PIN_MODE_INPUT(GPIOA_PIN8) | \
238 PIN_MODE_INPUT(GPIOA_PIN9) | \
239 PIN_MODE_INPUT(GPIOA_PIN10) | \
240 PIN_MODE_INPUT(GPIOA_USB_DM) | \
241 PIN_MODE_INPUT(GPIOA_USB_DP) | \
242 PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
243 PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
244 PIN_MODE_INPUT(GPIOA_PIN15))
245#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
246 PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
247 PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
248 PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
249 PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
250 PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
251 PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
252 PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
253 PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
254 PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
255 PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
256 PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
257 PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
258 PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
259 PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
260 PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
261#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | \
262 PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
263 PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
264 PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
265 PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
266 PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
267 PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
268 PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
269 PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
270 PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
271 PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
272 PIN_OSPEED_VERYLOW(GPIOA_USB_DM) | \
273 PIN_OSPEED_VERYLOW(GPIOA_USB_DP) | \
274 PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
275 PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
276 PIN_OSPEED_HIGH(GPIOA_PIN15))
277#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
278 PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
279 PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
280 PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
281 PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
282 PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
283 PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
284 PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
285 PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
286 PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
287 PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
288 PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
289 PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
290 PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
291 PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
292 PIN_PUPDR_PULLUP(GPIOA_PIN15))
293#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
294 PIN_ODR_HIGH(GPIOA_PIN1) | \
295 PIN_ODR_HIGH(GPIOA_PIN2) | \
296 PIN_ODR_HIGH(GPIOA_PIN3) | \
297 PIN_ODR_HIGH(GPIOA_PIN4) | \
298 PIN_ODR_HIGH(GPIOA_PIN5) | \
299 PIN_ODR_HIGH(GPIOA_PIN6) | \
300 PIN_ODR_HIGH(GPIOA_PIN7) | \
301 PIN_ODR_HIGH(GPIOA_PIN8) | \
302 PIN_ODR_HIGH(GPIOA_PIN9) | \
303 PIN_ODR_HIGH(GPIOA_PIN10) | \
304 PIN_ODR_HIGH(GPIOA_USB_DM) | \
305 PIN_ODR_HIGH(GPIOA_USB_DP) | \
306 PIN_ODR_HIGH(GPIOA_SWDIO) | \
307 PIN_ODR_HIGH(GPIOA_SWCLK) | \
308 PIN_ODR_HIGH(GPIOA_PIN15))
309#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \
310 PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
311 PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
312 PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
313 PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
314 PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
315 PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
316 PIN_AFIO_AF(GPIOA_PIN7, 0U))
317#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
318 PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
319 PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
320 PIN_AFIO_AF(GPIOA_USB_DM, 0U) | \
321 PIN_AFIO_AF(GPIOA_USB_DP, 0U) | \
322 PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
323 PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
324 PIN_AFIO_AF(GPIOA_PIN15, 0U))
325
326/*
327 * GPIOB setup:
328 *
329 * PB0 - PIN0 (input pullup).
330 * PB1 - PIN1 (input pullup).
331 * PB2 - PIN2 (input pullup).
332 * PB3 - PIN3 (input pullup).
333 * PB4 - PIN4 (input pullup).
334 * PB5 - PIN5 (input pullup).
335 * PB6 - PIN6 (input pullup).
336 * PB7 - PIN7 (input pullup).
337 * PB8 - PIN8 (input pullup).
338 * PB9 - PIN9 (input pullup).
339 * PB10 - PIN10 (input pullup).
340 * PB11 - PIN11 (input pullup).
341 * PB12 - PIN12 (input pullup).
342 * PB13 - SPI2_SCK (alternate 0).
343 * PB14 - SPI2_MISO (alternate 0).
344 * PB15 - SPI2_MOSI (alternate 0).
345 */
346#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
347 PIN_MODE_INPUT(GPIOB_PIN1) | \
348 PIN_MODE_INPUT(GPIOB_PIN2) | \
349 PIN_MODE_INPUT(GPIOB_PIN3) | \
350 PIN_MODE_INPUT(GPIOB_PIN4) | \
351 PIN_MODE_INPUT(GPIOB_PIN5) | \
352 PIN_MODE_INPUT(GPIOB_PIN6) | \
353 PIN_MODE_INPUT(GPIOB_PIN7) | \
354 PIN_MODE_INPUT(GPIOB_PIN8) | \
355 PIN_MODE_INPUT(GPIOB_PIN9) | \
356 PIN_MODE_INPUT(GPIOB_PIN10) | \
357 PIN_MODE_INPUT(GPIOB_PIN11) | \
358 PIN_MODE_INPUT(GPIOB_PIN12) | \
359 PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \
360 PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \
361 PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI))
362#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
363 PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
364 PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
365 PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
366 PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
367 PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
368 PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
369 PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
370 PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
371 PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
372 PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
373 PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
374 PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
375 PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \
376 PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \
377 PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI))
378#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
379 PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
380 PIN_OSPEED_HIGH(GPIOB_PIN2) | \
381 PIN_OSPEED_HIGH(GPIOB_PIN3) | \
382 PIN_OSPEED_HIGH(GPIOB_PIN4) | \
383 PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
384 PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
385 PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
386 PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
387 PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
388 PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
389 PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
390 PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
391 PIN_OSPEED_VERYLOW(GPIOB_SPI2_SCK) | \
392 PIN_OSPEED_VERYLOW(GPIOB_SPI2_MISO) | \
393 PIN_OSPEED_VERYLOW(GPIOB_SPI2_MOSI))
394#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
395 PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
396 PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
397 PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
398 PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
399 PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
400 PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
401 PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
402 PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
403 PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
404 PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
405 PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
406 PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
407 PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \
408 PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) | \
409 PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI))
410#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
411 PIN_ODR_HIGH(GPIOB_PIN1) | \
412 PIN_ODR_HIGH(GPIOB_PIN2) | \
413 PIN_ODR_HIGH(GPIOB_PIN3) | \
414 PIN_ODR_HIGH(GPIOB_PIN4) | \
415 PIN_ODR_HIGH(GPIOB_PIN5) | \
416 PIN_ODR_HIGH(GPIOB_PIN6) | \
417 PIN_ODR_HIGH(GPIOB_PIN7) | \
418 PIN_ODR_HIGH(GPIOB_PIN8) | \
419 PIN_ODR_HIGH(GPIOB_PIN9) | \
420 PIN_ODR_HIGH(GPIOB_PIN10) | \
421 PIN_ODR_HIGH(GPIOB_PIN11) | \
422 PIN_ODR_HIGH(GPIOB_PIN12) | \
423 PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \
424 PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \
425 PIN_ODR_HIGH(GPIOB_SPI2_MOSI))
426#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
427 PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
428 PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
429 PIN_AFIO_AF(GPIOB_PIN3, 0U) | \
430 PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
431 PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
432 PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
433 PIN_AFIO_AF(GPIOB_PIN7, 0U))
434#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
435 PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
436 PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
437 PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
438 PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
439 PIN_AFIO_AF(GPIOB_SPI2_SCK, 0U) | \
440 PIN_AFIO_AF(GPIOB_SPI2_MISO, 0U) | \
441 PIN_AFIO_AF(GPIOB_SPI2_MOSI, 0U))
442
443/*
444 * GPIOC setup:
445 *
446 * PC0 - MEMS_CS (output pushpull maximum).
447 * PC1 - PIN1 (input pullup).
448 * PC2 - PIN2 (input pullup).
449 * PC3 - PIN3 (input pullup).
450 * PC4 - PIN4 (input pullup).
451 * PC5 - PIN5 (input pullup).
452 * PC6 - LED_RED (output pushpull maximum).
453 * PC7 - LED_BLUE (output pushpull maximum).
454 * PC8 - LED_ORANGE (output pushpull maximum).
455 * PC9 - LED_GREEN (output pushpull maximum).
456 * PC10 - PIN10 (input pullup).
457 * PC11 - PIN11 (input pullup).
458 * PC12 - PIN12 (input pullup).
459 * PC13 - PIN13 (input pullup).
460 * PC14 - OSC32_IN (input floating).
461 * PC15 - OSC32_OUT (input floating).
462 */
463#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_MEMS_CS) | \
464 PIN_MODE_INPUT(GPIOC_PIN1) | \
465 PIN_MODE_INPUT(GPIOC_PIN2) | \
466 PIN_MODE_INPUT(GPIOC_PIN3) | \
467 PIN_MODE_INPUT(GPIOC_PIN4) | \
468 PIN_MODE_INPUT(GPIOC_PIN5) | \
469 PIN_MODE_OUTPUT(GPIOC_LED_RED) | \
470 PIN_MODE_OUTPUT(GPIOC_LED_BLUE) | \
471 PIN_MODE_OUTPUT(GPIOC_LED_ORANGE) | \
472 PIN_MODE_OUTPUT(GPIOC_LED_GREEN) | \
473 PIN_MODE_INPUT(GPIOC_PIN10) | \
474 PIN_MODE_INPUT(GPIOC_PIN11) | \
475 PIN_MODE_INPUT(GPIOC_PIN12) | \
476 PIN_MODE_INPUT(GPIOC_PIN13) | \
477 PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
478 PIN_MODE_INPUT(GPIOC_OSC32_OUT))
479#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_MEMS_CS) | \
480 PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
481 PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
482 PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
483 PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
484 PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
485 PIN_OTYPE_PUSHPULL(GPIOC_LED_RED) | \
486 PIN_OTYPE_PUSHPULL(GPIOC_LED_BLUE) | \
487 PIN_OTYPE_PUSHPULL(GPIOC_LED_ORANGE) | \
488 PIN_OTYPE_PUSHPULL(GPIOC_LED_GREEN) | \
489 PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
490 PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
491 PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
492 PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
493 PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
494 PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
495#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_MEMS_CS) | \
496 PIN_OSPEED_VERYLOW(GPIOC_PIN1) | \
497 PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
498 PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
499 PIN_OSPEED_VERYLOW(GPIOC_PIN4) | \
500 PIN_OSPEED_VERYLOW(GPIOC_PIN5) | \
501 PIN_OSPEED_HIGH(GPIOC_LED_RED) | \
502 PIN_OSPEED_HIGH(GPIOC_LED_BLUE) | \
503 PIN_OSPEED_HIGH(GPIOC_LED_ORANGE) | \
504 PIN_OSPEED_HIGH(GPIOC_LED_GREEN) | \
505 PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
506 PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
507 PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
508 PIN_OSPEED_VERYLOW(GPIOC_PIN13) | \
509 PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
510 PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
511#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_MEMS_CS) | \
512 PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
513 PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
514 PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
515 PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
516 PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
517 PIN_PUPDR_FLOATING(GPIOC_LED_RED) | \
518 PIN_PUPDR_FLOATING(GPIOC_LED_BLUE) | \
519 PIN_PUPDR_FLOATING(GPIOC_LED_ORANGE) | \
520 PIN_PUPDR_FLOATING(GPIOC_LED_GREEN) | \
521 PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
522 PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
523 PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
524 PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
525 PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
526 PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
527#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_MEMS_CS) | \
528 PIN_ODR_HIGH(GPIOC_PIN1) | \
529 PIN_ODR_HIGH(GPIOC_PIN2) | \
530 PIN_ODR_HIGH(GPIOC_PIN3) | \
531 PIN_ODR_HIGH(GPIOC_PIN4) | \
532 PIN_ODR_HIGH(GPIOC_PIN5) | \
533 PIN_ODR_LOW(GPIOC_LED_RED) | \
534 PIN_ODR_LOW(GPIOC_LED_BLUE) | \
535 PIN_ODR_LOW(GPIOC_LED_ORANGE) | \
536 PIN_ODR_LOW(GPIOC_LED_GREEN) | \
537 PIN_ODR_HIGH(GPIOC_PIN10) | \
538 PIN_ODR_HIGH(GPIOC_PIN11) | \
539 PIN_ODR_HIGH(GPIOC_PIN12) | \
540 PIN_ODR_HIGH(GPIOC_PIN13) | \
541 PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
542 PIN_ODR_HIGH(GPIOC_OSC32_OUT))
543#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_MEMS_CS, 0U) | \
544 PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
545 PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
546 PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
547 PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
548 PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
549 PIN_AFIO_AF(GPIOC_LED_RED, 0U) | \
550 PIN_AFIO_AF(GPIOC_LED_BLUE, 0U))
551#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED_ORANGE, 0U) | \
552 PIN_AFIO_AF(GPIOC_LED_GREEN, 0U) | \
553 PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
554 PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
555 PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
556 PIN_AFIO_AF(GPIOC_PIN13, 0U) | \
557 PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
558 PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
559
560/*
561 * GPIOD setup:
562 *
563 * PD0 - PIN0 (input pullup).
564 * PD1 - PIN1 (input pullup).
565 * PD2 - PIN2 (input pullup).
566 * PD3 - PIN3 (input pullup).
567 * PD4 - PIN4 (input pullup).
568 * PD5 - PIN5 (input pullup).
569 * PD6 - PIN6 (input pullup).
570 * PD7 - PIN7 (input pullup).
571 * PD8 - PIN8 (input pullup).
572 * PD9 - PIN9 (input pullup).
573 * PD10 - PIN10 (input pullup).
574 * PD11 - PIN11 (input pullup).
575 * PD12 - PIN12 (input pullup).
576 * PD13 - PIN13 (input pullup).
577 * PD14 - PIN14 (input pullup).
578 * PD15 - PIN15 (input pullup).
579 */
580#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
581 PIN_MODE_INPUT(GPIOD_PIN1) | \
582 PIN_MODE_INPUT(GPIOD_PIN2) | \
583 PIN_MODE_INPUT(GPIOD_PIN3) | \
584 PIN_MODE_INPUT(GPIOD_PIN4) | \
585 PIN_MODE_INPUT(GPIOD_PIN5) | \
586 PIN_MODE_INPUT(GPIOD_PIN6) | \
587 PIN_MODE_INPUT(GPIOD_PIN7) | \
588 PIN_MODE_INPUT(GPIOD_PIN8) | \
589 PIN_MODE_INPUT(GPIOD_PIN9) | \
590 PIN_MODE_INPUT(GPIOD_PIN10) | \
591 PIN_MODE_INPUT(GPIOD_PIN11) | \
592 PIN_MODE_INPUT(GPIOD_PIN12) | \
593 PIN_MODE_INPUT(GPIOD_PIN13) | \
594 PIN_MODE_INPUT(GPIOD_PIN14) | \
595 PIN_MODE_INPUT(GPIOD_PIN15))
596#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
597 PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
598 PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
599 PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
600 PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
601 PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
602 PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
603 PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
604 PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
605 PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
606 PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
607 PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
608 PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
609 PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
610 PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
611 PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
612#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
613 PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
614 PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
615 PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
616 PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
617 PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
618 PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
619 PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
620 PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \
621 PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \
622 PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
623 PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
624 PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
625 PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
626 PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
627 PIN_OSPEED_VERYLOW(GPIOD_PIN15))
628#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
629 PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
630 PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
631 PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
632 PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
633 PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
634 PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
635 PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
636 PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
637 PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
638 PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
639 PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
640 PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
641 PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
642 PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
643 PIN_PUPDR_PULLUP(GPIOD_PIN15))
644#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
645 PIN_ODR_HIGH(GPIOD_PIN1) | \
646 PIN_ODR_HIGH(GPIOD_PIN2) | \
647 PIN_ODR_HIGH(GPIOD_PIN3) | \
648 PIN_ODR_HIGH(GPIOD_PIN4) | \
649 PIN_ODR_HIGH(GPIOD_PIN5) | \
650 PIN_ODR_HIGH(GPIOD_PIN6) | \
651 PIN_ODR_HIGH(GPIOD_PIN7) | \
652 PIN_ODR_HIGH(GPIOD_PIN8) | \
653 PIN_ODR_HIGH(GPIOD_PIN9) | \
654 PIN_ODR_HIGH(GPIOD_PIN10) | \
655 PIN_ODR_HIGH(GPIOD_PIN11) | \
656 PIN_ODR_HIGH(GPIOD_PIN12) | \
657 PIN_ODR_HIGH(GPIOD_PIN13) | \
658 PIN_ODR_HIGH(GPIOD_PIN14) | \
659 PIN_ODR_HIGH(GPIOD_PIN15))
660#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
661 PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
662 PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
663 PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
664 PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
665 PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
666 PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
667 PIN_AFIO_AF(GPIOD_PIN7, 0U))
668#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
669 PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
670 PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
671 PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
672 PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
673 PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
674 PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
675 PIN_AFIO_AF(GPIOD_PIN15, 0U))
676
677/*
678 * GPIOE setup:
679 *
680 * PE0 - PIN0 (input pullup).
681 * PE1 - PIN1 (input pullup).
682 * PE2 - PIN2 (input pullup).
683 * PE3 - PIN3 (input pullup).
684 * PE4 - PIN4 (input pullup).
685 * PE5 - PIN5 (input pullup).
686 * PE6 - PIN6 (input pullup).
687 * PE7 - PIN7 (input pullup).
688 * PE8 - PIN8 (input pullup).
689 * PE9 - PIN9 (input pullup).
690 * PE10 - PIN10 (input pullup).
691 * PE11 - PIN11 (input pullup).
692 * PE12 - PIN12 (input pullup).
693 * PE13 - PIN13 (input pullup).
694 * PE14 - PIN14 (input pullup).
695 * PE15 - PIN15 (input pullup).
696 */
697#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
698 PIN_MODE_INPUT(GPIOE_PIN1) | \
699 PIN_MODE_INPUT(GPIOE_PIN2) | \
700 PIN_MODE_INPUT(GPIOE_PIN3) | \
701 PIN_MODE_INPUT(GPIOE_PIN4) | \
702 PIN_MODE_INPUT(GPIOE_PIN5) | \
703 PIN_MODE_INPUT(GPIOE_PIN6) | \
704 PIN_MODE_INPUT(GPIOE_PIN7) | \
705 PIN_MODE_INPUT(GPIOE_PIN8) | \
706 PIN_MODE_INPUT(GPIOE_PIN9) | \
707 PIN_MODE_INPUT(GPIOE_PIN10) | \
708 PIN_MODE_INPUT(GPIOE_PIN11) | \
709 PIN_MODE_INPUT(GPIOE_PIN12) | \
710 PIN_MODE_INPUT(GPIOE_PIN13) | \
711 PIN_MODE_INPUT(GPIOE_PIN14) | \
712 PIN_MODE_INPUT(GPIOE_PIN15))
713#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
714 PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
715 PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
716 PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
717 PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
718 PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
719 PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
720 PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
721 PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
722 PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
723 PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
724 PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
725 PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
726 PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
727 PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
728 PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
729#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
730 PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
731 PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
732 PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
733 PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
734 PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
735 PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
736 PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
737 PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
738 PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
739 PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
740 PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
741 PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
742 PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
743 PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
744 PIN_OSPEED_VERYLOW(GPIOE_PIN15))
745#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
746 PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
747 PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
748 PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
749 PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
750 PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
751 PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
752 PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
753 PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
754 PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
755 PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
756 PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
757 PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
758 PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
759 PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
760 PIN_PUPDR_PULLUP(GPIOE_PIN15))
761#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
762 PIN_ODR_HIGH(GPIOE_PIN1) | \
763 PIN_ODR_HIGH(GPIOE_PIN2) | \
764 PIN_ODR_HIGH(GPIOE_PIN3) | \
765 PIN_ODR_HIGH(GPIOE_PIN4) | \
766 PIN_ODR_HIGH(GPIOE_PIN5) | \
767 PIN_ODR_HIGH(GPIOE_PIN6) | \
768 PIN_ODR_HIGH(GPIOE_PIN7) | \
769 PIN_ODR_HIGH(GPIOE_PIN8) | \
770 PIN_ODR_HIGH(GPIOE_PIN9) | \
771 PIN_ODR_HIGH(GPIOE_PIN10) | \
772 PIN_ODR_HIGH(GPIOE_PIN11) | \
773 PIN_ODR_HIGH(GPIOE_PIN12) | \
774 PIN_ODR_HIGH(GPIOE_PIN13) | \
775 PIN_ODR_HIGH(GPIOE_PIN14) | \
776 PIN_ODR_HIGH(GPIOE_PIN15))
777#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
778 PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
779 PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
780 PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
781 PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
782 PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
783 PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
784 PIN_AFIO_AF(GPIOE_PIN7, 0U))
785#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
786 PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
787 PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
788 PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
789 PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
790 PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
791 PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
792 PIN_AFIO_AF(GPIOE_PIN15, 0U))
793
794/*
795 * GPIOF setup:
796 *
797 * PF0 - OSC_IN (input floating).
798 * PF1 - OSC_OUT (input floating).
799 * PF2 - PIN2 (input pullup).
800 * PF3 - PIN3 (input pullup).
801 * PF4 - PIN4 (input pullup).
802 * PF5 - PIN5 (input pullup).
803 * PF6 - PIN6 (input pullup).
804 * PF7 - PIN7 (input pullup).
805 * PF8 - PIN8 (input pullup).
806 * PF9 - PIN9 (input pullup).
807 * PF10 - PIN10 (input pullup).
808 * PF11 - PIN11 (input pullup).
809 * PF12 - PIN12 (input pullup).
810 * PF13 - PIN13 (input pullup).
811 * PF14 - PIN14 (input pullup).
812 * PF15 - PIN15 (input pullup).
813 */
814#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
815 PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
816 PIN_MODE_INPUT(GPIOF_PIN2) | \
817 PIN_MODE_INPUT(GPIOF_PIN3) | \
818 PIN_MODE_INPUT(GPIOF_PIN4) | \
819 PIN_MODE_INPUT(GPIOF_PIN5) | \
820 PIN_MODE_INPUT(GPIOF_PIN6) | \
821 PIN_MODE_INPUT(GPIOF_PIN7) | \
822 PIN_MODE_INPUT(GPIOF_PIN8) | \
823 PIN_MODE_INPUT(GPIOF_PIN9) | \
824 PIN_MODE_INPUT(GPIOF_PIN10) | \
825 PIN_MODE_INPUT(GPIOF_PIN11) | \
826 PIN_MODE_INPUT(GPIOF_PIN12) | \
827 PIN_MODE_INPUT(GPIOF_PIN13) | \
828 PIN_MODE_INPUT(GPIOF_PIN14) | \
829 PIN_MODE_INPUT(GPIOF_PIN15))
830#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
831 PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
832 PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
833 PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
834 PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
835 PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
836 PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
837 PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
838 PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
839 PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
840 PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
841 PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
842 PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
843 PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
844 PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
845 PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
846#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_OSC_IN) | \
847 PIN_OSPEED_VERYLOW(GPIOF_OSC_OUT) | \
848 PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
849 PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
850 PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
851 PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
852 PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
853 PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
854 PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
855 PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
856 PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
857 PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
858 PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
859 PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
860 PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
861 PIN_OSPEED_VERYLOW(GPIOF_PIN15))
862#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
863 PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
864 PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
865 PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
866 PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
867 PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
868 PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
869 PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
870 PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
871 PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
872 PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
873 PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
874 PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
875 PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
876 PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
877 PIN_PUPDR_PULLUP(GPIOF_PIN15))
878#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
879 PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
880 PIN_ODR_HIGH(GPIOF_PIN2) | \
881 PIN_ODR_HIGH(GPIOF_PIN3) | \
882 PIN_ODR_HIGH(GPIOF_PIN4) | \
883 PIN_ODR_HIGH(GPIOF_PIN5) | \
884 PIN_ODR_HIGH(GPIOF_PIN6) | \
885 PIN_ODR_HIGH(GPIOF_PIN7) | \
886 PIN_ODR_HIGH(GPIOF_PIN8) | \
887 PIN_ODR_HIGH(GPIOF_PIN9) | \
888 PIN_ODR_HIGH(GPIOF_PIN10) | \
889 PIN_ODR_HIGH(GPIOF_PIN11) | \
890 PIN_ODR_HIGH(GPIOF_PIN12) | \
891 PIN_ODR_HIGH(GPIOF_PIN13) | \
892 PIN_ODR_HIGH(GPIOF_PIN14) | \
893 PIN_ODR_HIGH(GPIOF_PIN15))
894#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \
895 PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \
896 PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
897 PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
898 PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
899 PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
900 PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
901 PIN_AFIO_AF(GPIOF_PIN7, 0U))
902#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
903 PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
904 PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
905 PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
906 PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
907 PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
908 PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
909 PIN_AFIO_AF(GPIOF_PIN15, 0U))
910
911
912#if !defined(_FROM_ASM_)
913#ifdef __cplusplus
914extern "C" {
915#endif
916 void boardInit(void);
917#ifdef __cplusplus
918}
919#endif
920#endif /* _FROM_ASM_ */
921
922#endif /* BOARD_H */
diff --git a/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.mk b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.mk
new file mode 100644
index 000000000..b98dcdd26
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
1# List of all the board related files.
2BOARDSRC = $(BOARD_PATH)/boards/ST_STM32F072B_DISCOVERY/board.c
3
4# Required include directories
5BOARDINC = $(BOARD_PATH)/boards/ST_STM32F072B_DISCOVERY
diff --git a/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..9c7cf4fd7
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,703 @@
1<?xml version="1.0" encoding="UTF-8"?>
2<!-- STM32F0xx board Template -->
3<board
4 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
5 xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd">
6 <configuration_settings>
7 <templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
8 <output_path>..</output_path>
9 <hal_version>3.0.x</hal_version>
10 </configuration_settings>
11 <board_name>ST STM32F072B-Discovery</board_name>
12 <board_id>ST_STM32F072B_DISCOVERY</board_id>
13 <board_functions></board_functions>
14 <subtype>STM32F072xB</subtype>
15 <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
16 LSEBypass="false" LSEDrive="3 High Drive (default)" />
17 <ports>
18 <GPIOA>
19 <pin0
20 ID="BUTTON"
21 Type="PushPull"
22 Speed="Minimum"
23 Resistor="Floating"
24 Level="High"
25 Mode="Input"
26 Alternate="0" />
27 <pin1
28 ID=""
29 Type="PushPull"
30 Speed="Minimum"
31 Resistor="PullUp"
32 Level="High"
33 Mode="Input"
34 Alternate="0" />
35 <pin2
36 ID=""
37 Type="PushPull"
38 Speed="Minimum"
39 Resistor="PullUp"
40 Level="High"
41 Mode="Input"
42 Alternate="0" />
43 <pin3
44 ID=""
45 Type="PushPull"
46 Speed="Minimum"
47 Resistor="PullUp"
48 Level="High"
49 Mode="Input"
50 Alternate="0" />
51 <pin4
52 ID=""
53 Type="PushPull"
54 Speed="Minimum"
55 Resistor="PullUp"
56 Level="High"
57 Mode="Input"
58 Alternate="0" />
59 <pin5
60 ID=""
61 Type="PushPull"
62 Speed="Minimum"
63 Resistor="PullUp"
64 Level="High"
65 Mode="Input"
66 Alternate="0" />
67 <pin6
68 ID=""
69 Type="PushPull"
70 Speed="Minimum"
71 Resistor="PullUp"
72 Level="High"
73 Mode="Input"
74 Alternate="0" />
75 <pin7
76 ID=""
77 Type="PushPull"
78 Speed="Minimum"
79 Resistor="PullUp"
80 Level="High"
81 Mode="Input"
82 Alternate="0" />
83 <pin8
84 ID=""
85 Type="PushPull"
86 Speed="Minimum"
87 Resistor="PullUp"
88 Level="High"
89 Mode="Input"
90 Alternate="0" />
91 <pin9
92 ID=""
93 Type="PushPull"
94 Speed="Minimum"
95 Resistor="PullUp"
96 Level="High"
97 Mode="Input"
98 Alternate="0" />
99 <pin10
100 ID=""
101 Type="PushPull"
102 Speed="Minimum"
103 Resistor="PullUp"
104 Level="High"
105 Mode="Input"
106 Alternate="0" />
107 <pin11
108 ID="USB_DM"
109 Type="PushPull"
110 Speed="Minimum"
111 Resistor="Floating"
112 Level="High"
113 Mode="Input"
114 Alternate="0" />
115 <pin12
116 ID="USB_DP"
117 Type="PushPull"
118 Speed="Minimum"
119 Resistor="Floating"
120 Level="High"
121 Mode="Input"
122 Alternate="0" />
123 <pin13
124 ID="SWDIO"
125 Type="PushPull"
126 Speed="Maximum"
127 Resistor="PullUp"
128 Level="High"
129 Mode="Alternate"
130 Alternate="0" />
131 <pin14
132 ID="SWCLK"
133 Type="PushPull"
134 Speed="Maximum"
135 Resistor="PullDown"
136 Level="High"
137 Mode="Alternate"
138 Alternate="0" />
139 <pin15
140 ID=""
141 Type="PushPull"
142 Speed="Maximum"
143 Resistor="PullUp"
144 Level="High"
145 Mode="Input"
146 Alternate="0" />
147 </GPIOA>
148 <GPIOB>
149 <pin0
150 ID=""
151 Type="PushPull"
152 Speed="Minimum"
153 Resistor="PullUp"
154 Level="High"
155 Mode="Input"
156 Alternate="0" />
157 <pin1
158 ID=""
159 Type="PushPull"
160 Speed="Minimum"
161 Resistor="PullUp"
162 Level="High"
163 Mode="Input"
164 Alternate="0" />
165 <pin2
166 ID=""
167 Type="PushPull"
168 Speed="Maximum"
169 Resistor="PullUp"
170 Level="High"
171 Mode="Input"
172 Alternate="0" />
173 <pin3
174 ID=""
175 Type="PushPull"
176 Speed="Maximum"
177 Resistor="PullUp"
178 Level="High"
179 Mode="Input"
180 Alternate="0" />
181 <pin4
182 ID=""
183 Type="PushPull"
184 Speed="Maximum"
185 Resistor="PullUp"
186 Level="High"
187 Mode="Input"
188 Alternate="0" />
189 <pin5
190 ID=""
191 Type="PushPull"
192 Speed="Minimum"
193 Resistor="PullUp"
194 Level="High"
195 Mode="Input"
196 Alternate="0" />
197 <pin6
198 ID=""
199 Type="PushPull"
200 Speed="Minimum"
201 Resistor="PullUp"
202 Level="High"
203 Mode="Input"
204 Alternate="0" />
205 <pin7
206 ID=""
207 Type="PushPull"
208 Speed="Minimum"
209 Resistor="PullUp"
210 Level="High"
211 Mode="Input"
212 Alternate="0" />
213 <pin8
214 ID=""
215 Type="PushPull"
216 Speed="Minimum"
217 Resistor="PullUp"
218 Level="High"
219 Mode="Input"
220 Alternate="0" />
221 <pin9
222 ID=""
223 Type="PushPull"
224 Speed="Minimum"
225 Resistor="PullUp"
226 Level="High"
227 Mode="Input"
228 Alternate="0" />
229 <pin10
230 ID=""
231 Type="PushPull"
232 Speed="Minimum"
233 Resistor="PullUp"
234 Level="High"
235 Mode="Input"
236 Alternate="0" />
237 <pin11
238 ID=""
239 Type="PushPull"
240 Speed="Minimum"
241 Resistor="PullUp"
242 Level="High"
243 Mode="Input"
244 Alternate="0" />
245 <pin12
246 ID=""
247 Type="PushPull"
248 Speed="Minimum"
249 Resistor="PullUp"
250 Level="High"
251 Mode="Input"
252 Alternate="0" />
253 <pin13
254 ID="SPI2_SCK"
255 Type="PushPull"
256 Speed="Minimum"
257 Resistor="Floating"
258 Level="High"
259 Mode="Alternate"
260 Alternate="0" />
261 <pin14
262 ID="SPI2_MISO"
263 Type="PushPull"
264 Speed="Minimum"
265 Resistor="Floating"
266 Level="High"
267 Mode="Alternate"
268 Alternate="0" />
269 <pin15
270 ID="SPI2_MOSI"
271 Type="PushPull"
272 Speed="Minimum"
273 Resistor="Floating"
274 Level="High"
275 Mode="Alternate"
276 Alternate="0" />
277 </GPIOB>
278 <GPIOC>
279 <pin0
280 ID="MEMS_CS"
281 Type="PushPull"
282 Speed="Maximum"
283 Resistor="Floating"
284 Level="High"
285 Mode="Output"
286 Alternate="0" />
287 <pin1
288 ID=""
289 Type="PushPull"
290 Speed="Minimum"
291 Resistor="PullUp"
292 Level="High"
293 Mode="Input"
294 Alternate="0" />
295 <pin2
296 ID=""
297 Type="PushPull"
298 Speed="Minimum"
299 Resistor="PullUp"
300 Level="High"
301 Mode="Input"
302 Alternate="0" />
303 <pin3
304 ID=""
305 Type="PushPull"
306 Speed="Minimum"
307 Resistor="PullUp"
308 Level="High"
309 Mode="Input"
310 Alternate="0" />
311 <pin4
312 ID=""
313 Type="PushPull"
314 Speed="Minimum"
315 Resistor="PullUp"
316 Level="High"
317 Mode="Input"
318 Alternate="0" />
319 <pin5
320 ID=""
321 Type="PushPull"
322 Speed="Minimum"
323 Resistor="PullUp"
324 Level="High"
325 Mode="Input"
326 Alternate="0" />
327 <pin6
328 ID="LED_RED"
329 Type="PushPull"
330 Speed="Maximum"
331 Resistor="Floating"
332 Level="Low"
333 Mode="Output"
334 Alternate="0" />
335 <pin7
336 ID="LED_BLUE"
337 Type="PushPull"
338 Speed="Maximum"
339 Resistor="Floating"
340 Level="Low"
341 Mode="Output"
342 Alternate="0" />
343 <pin8
344 ID="LED_ORANGE"
345 Type="PushPull"
346 Speed="Maximum"
347 Resistor="Floating"
348 Level="Low"
349 Mode="Output"
350 Alternate="0" ></pin8>
351 <pin9
352 ID="LED_GREEN"
353 Type="PushPull"
354 Speed="Maximum"
355 Resistor="Floating"
356 Level="Low"
357 Mode="Output"
358 Alternate="0" />
359 <pin10
360 ID=""
361 Type="PushPull"
362 Speed="Minimum"
363 Resistor="PullUp"
364 Level="High"
365 Mode="Input"
366 Alternate="0" />
367 <pin11
368 ID=""
369 Type="PushPull"
370 Speed="Minimum"
371 Resistor="PullUp"
372 Level="High"
373 Mode="Input"
374 Alternate="0" />
375 <pin12
376 ID=""
377 Type="PushPull"
378 Speed="Minimum"
379 Resistor="PullUp"
380 Level="High"
381 Mode="Input"
382 Alternate="0" />
383 <pin13
384 ID=""
385 Type="PushPull"
386 Speed="Minimum"
387 Resistor="PullUp"
388 Level="High"
389 Mode="Input"
390 Alternate="0" />
391 <pin14
392 ID="OSC32_IN"
393 Type="PushPull"
394 Speed="Maximum"
395 Resistor="Floating"
396 Level="High"
397 Mode="Input"
398 Alternate="0" />
399 <pin15
400 ID="OSC32_OUT"
401 Type="PushPull"
402 Speed="Maximum"
403 Resistor="Floating"
404 Level="High"
405 Mode="Input"
406 Alternate="0" />
407 </GPIOC>
408 <GPIOD>
409 <pin0
410 ID=""
411 Type="PushPull"
412 Speed="Minimum"
413 Resistor="PullUp"
414 Level="High"
415 Mode="Input"
416 Alternate="0" />
417 <pin1
418 ID=""
419 Type="PushPull"
420 Speed="Minimum"
421 Resistor="PullUp"
422 Level="High"
423 Mode="Input"
424 Alternate="0" />
425 <pin2
426 ID=""
427 Type="PushPull"
428 Speed="Minimum"
429 Resistor="PullUp"
430 Level="High"
431 Mode="Input"
432 Alternate="0" />
433 <pin3
434 ID=""
435 Type="PushPull"
436 Speed="Minimum"
437 Resistor="PullUp"
438 Level="High"
439 Mode="Input"
440 Alternate="0" />
441 <pin4
442 ID=""
443 Type="PushPull"
444 Speed="Minimum"
445 Resistor="PullUp"
446 Level="High"
447 Mode="Input"
448 Alternate="0" />
449 <pin5
450 ID=""
451 Type="PushPull"
452 Speed="Minimum"
453 Resistor="PullUp"
454 Level="High"
455 Mode="Input"
456 Alternate="0" />
457 <pin6
458 ID=""
459 Type="PushPull"
460 Speed="Minimum"
461 Resistor="PullUp"
462 Level="High"
463 Mode="Input"
464 Alternate="0" />
465 <pin7
466 ID=""
467 Type="PushPull"
468 Speed="Minimum"
469 Resistor="PullUp"
470 Level="High"
471 Mode="Input"
472 Alternate="0" />
473 <pin8
474 ID=""
475 Type="PushPull"
476 Speed="Minimum"
477 Resistor="PullUp"
478 Level="High"
479 Mode="Input"
480 Alternate="0" />
481 <pin9
482 ID=""
483 Type="PushPull"
484 Speed="Minimum"
485 Resistor="PullUp"
486 Level="High"
487 Mode="Input"
488 Alternate="0" />
489 <pin10
490 ID=""
491 Type="PushPull"
492 Speed="Minimum"
493 Resistor="PullUp"
494 Level="High"
495 Mode="Input"
496 Alternate="0" />
497 <pin11
498 ID=""
499 Type="PushPull"
500 Speed="Minimum"
501 Resistor="PullUp"
502 Level="High"
503 Mode="Input"
504 Alternate="0" />
505 <pin12
506 ID=""
507 Type="PushPull"
508 Speed="Minimum"
509 Resistor="PullUp"
510 Level="High"
511 Mode="Input"
512 Alternate="0" />
513 <pin13
514 ID=""
515 Type="PushPull"
516 Speed="Minimum"
517 Resistor="PullUp"
518 Level="High"
519 Mode="Input"
520 Alternate="0" />
521 <pin14
522 ID=""
523 Type="PushPull"
524 Speed="Minimum"
525 Resistor="PullUp"
526 Level="High"
527 Mode="Input"
528 Alternate="0" />
529 <pin15
530 ID=""
531 Type="PushPull"
532 Speed="Minimum"
533 Resistor="PullUp"
534 Level="High"
535 Mode="Input"
536 Alternate="0" />
537 </GPIOD>
538 <GPIOE>
539 <pin0 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
540 Level="High" Mode="Input" Alternate="0" />
541 <pin1 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
542 Level="High" Mode="Input" Alternate="0" />
543 <pin2 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
544 Level="High" Mode="Input" Alternate="0" />
545 <pin3 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
546 Level="High" Mode="Input" Alternate="0" />
547 <pin4 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
548 Level="High" Mode="Input" Alternate="0" />
549 <pin5 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
550 Level="High" Mode="Input" Alternate="0" />
551 <pin6 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
552 Level="High" Mode="Input" Alternate="0" />
553 <pin7 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
554 Level="High" Mode="Input" Alternate="0" />
555 <pin8 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
556 Level="High" Mode="Input" Alternate="0" />
557 <pin9 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
558 Level="High" Mode="Input" Alternate="0" />
559 <pin10 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
560 Level="High" Mode="Input" Alternate="0" />
561 <pin11 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
562 Level="High" Mode="Input" Alternate="0" />
563 <pin12 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
564 Level="High" Mode="Input" Alternate="0" />
565 <pin13 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
566 Level="High" Mode="Input" Alternate="0" />
567 <pin14 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
568 Level="High" Mode="Input" Alternate="0" />
569 <pin15 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
570 Level="High" Mode="Input" Alternate="0" />
571 </GPIOE>
572 <GPIOF>
573 <pin0
574 ID="OSC_IN"
575 Type="PushPull"
576 Speed="Minimum"
577 Resistor="Floating"
578 Level="High"
579 Mode="Input"
580 Alternate="0" />
581 <pin1
582 ID="OSC_OUT"
583 Type="PushPull"
584 Speed="Minimum"
585 Resistor="Floating"
586 Level="High"
587 Mode="Input"
588 Alternate="0" />
589 <pin2
590 ID=""
591 Type="PushPull"
592 Speed="Minimum"
593 Resistor="PullUp"
594 Level="High"
595 Mode="Input"
596 Alternate="0" />
597 <pin3
598 ID=""
599 Type="PushPull"
600 Speed="Minimum"
601 Resistor="PullUp"
602 Level="High"
603 Mode="Input"
604 Alternate="0" />
605 <pin4
606 ID=""
607 Type="PushPull"
608 Speed="Minimum"
609 Resistor="PullUp"
610 Level="High"
611 Mode="Input"
612 Alternate="0" />
613 <pin5
614 ID=""
615 Type="PushPull"
616 Speed="Minimum"
617 Resistor="PullUp"
618 Level="High"
619 Mode="Input"
620 Alternate="0" />
621 <pin6
622 ID=""
623 Type="PushPull"
624 Speed="Minimum"
625 Resistor="PullUp"
626 Level="High"
627 Mode="Input"
628 Alternate="0" />
629 <pin7
630 ID=""
631 Type="PushPull"
632 Speed="Minimum"
633 Resistor="PullUp"
634 Level="High"
635 Mode="Input"
636 Alternate="0" />
637 <pin8
638 ID=""
639 Type="PushPull"
640 Speed="Minimum"
641 Resistor="PullUp"
642 Level="High"
643 Mode="Input"
644 Alternate="0" />
645 <pin9
646 ID=""
647 Type="PushPull"
648 Speed="Minimum"
649 Resistor="PullUp"
650 Level="High"
651 Mode="Input"
652 Alternate="0" />
653 <pin10
654 ID=""
655 Type="PushPull"
656 Speed="Minimum"
657 Resistor="PullUp"
658 Level="High"
659 Mode="Input"
660 Alternate="0" />
661 <pin11
662 ID=""
663 Type="PushPull"
664 Speed="Minimum"
665 Resistor="PullUp"
666 Level="High"
667 Mode="Input"
668 Alternate="0" />
669 <pin12
670 ID=""
671 Type="PushPull"
672 Speed="Minimum"
673 Resistor="PullUp"
674 Level="High"
675 Mode="Input"
676 Alternate="0" />
677 <pin13
678 ID=""
679 Type="PushPull"
680 Speed="Minimum"
681 Resistor="PullUp"
682 Level="High"
683 Mode="Input"
684 Alternate="0" />
685 <pin14
686 ID=""
687 Type="PushPull"
688 Speed="Minimum"
689 Resistor="PullUp"
690 Level="High"
691 Mode="Input"
692 Alternate="0" />
693 <pin15
694 ID=""
695 Type="PushPull"
696 Speed="Minimum"
697 Resistor="PullUp"
698 Level="High"
699 Mode="Input"
700 Alternate="0" />
701 </GPIOF>
702 </ports>
703</board>
diff --git a/keyboards/cannonkeys/chimera65/bootloader_defs.h b/keyboards/cannonkeys/chimera65/bootloader_defs.h
new file mode 100644
index 000000000..02c48c4e6
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/bootloader_defs.h
@@ -0,0 +1,7 @@
1/* Address for jumping to bootloader on STM32 chips. */
2/* It is chip dependent, the correct number can be looked up here (page 175):
3 * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
4 * This also requires a patch to chibios:
5 * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
6 */
7#define STM32_BOOTLOADER_ADDRESS 0x1FFFC800
diff --git a/keyboards/cannonkeys/chimera65/chconf.h b/keyboards/cannonkeys/chimera65/chconf.h
new file mode 100644
index 000000000..99fa8ce39
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/chconf.h
@@ -0,0 +1,524 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file templates/chconf.h
19 * @brief Configuration file template.
20 * @details A copy of this file must be placed in each project directory, it
21 * contains the application specific kernel settings.
22 *
23 * @addtogroup config
24 * @details Kernel related settings and hooks.
25 * @{
26 */
27
28#ifndef CHCONF_H
29#define CHCONF_H
30
31#define _CHIBIOS_RT_CONF_
32
33/*===========================================================================*/
34/**
35 * @name System timers settings
36 * @{
37 */
38/*===========================================================================*/
39
40/**
41 * @brief System time counter resolution.
42 * @note Allowed values are 16 or 32 bits.
43 */
44#define CH_CFG_ST_RESOLUTION 32
45
46/**
47 * @brief System tick frequency.
48 * @details Frequency of the system timer that drives the system ticks. This
49 * setting also defines the system tick time unit.
50 */
51#define CH_CFG_ST_FREQUENCY 10000
52
53/**
54 * @brief Time delta constant for the tick-less mode.
55 * @note If this value is zero then the system uses the classic
56 * periodic tick. This value represents the minimum number
57 * of ticks that is safe to specify in a timeout directive.
58 * The value one is not valid, timeouts are rounded up to
59 * this value.
60 */
61#define CH_CFG_ST_TIMEDELTA 2
62
63/** @} */
64
65/*===========================================================================*/
66/**
67 * @name Kernel parameters and options
68 * @{
69 */
70/*===========================================================================*/
71
72/**
73 * @brief Round robin interval.
74 * @details This constant is the number of system ticks allowed for the
75 * threads before preemption occurs. Setting this value to zero
76 * disables the preemption for threads with equal priority and the
77 * round robin becomes cooperative. Note that higher priority
78 * threads can still preempt, the kernel is always preemptive.
79 * @note Disabling the round robin preemption makes the kernel more compact
80 * and generally faster.
81 * @note The round robin preemption is not supported in tickless mode and
82 * must be set to zero in that case.
83 */
84#define CH_CFG_TIME_QUANTUM 0
85
86/**
87 * @brief Managed RAM size.
88 * @details Size of the RAM area to be managed by the OS. If set to zero
89 * then the whole available RAM is used. The core memory is made
90 * available to the heap allocator and/or can be used directly through
91 * the simplified core memory allocator.
92 *
93 * @note In order to let the OS manage the whole RAM the linker script must
94 * provide the @p __heap_base__ and @p __heap_end__ symbols.
95 * @note Requires @p CH_CFG_USE_MEMCORE.
96 */
97#define CH_CFG_MEMCORE_SIZE 0
98
99/**
100 * @brief Idle thread automatic spawn suppression.
101 * @details When this option is activated the function @p chSysInit()
102 * does not spawn the idle thread. The application @p main()
103 * function becomes the idle thread and must implement an
104 * infinite loop.
105 */
106#define CH_CFG_NO_IDLE_THREAD FALSE
107
108/* Use __WFI in the idle thread for waiting. Does lower the power
109 * consumption. */
110#define CORTEX_ENABLE_WFI_IDLE TRUE
111
112/** @} */
113
114/*===========================================================================*/
115/**
116 * @name Performance options
117 * @{
118 */
119/*===========================================================================*/
120
121/**
122 * @brief OS optimization.
123 * @details If enabled then time efficient rather than space efficient code
124 * is used when two possible implementations exist.
125 *
126 * @note This is not related to the compiler optimization options.
127 * @note The default is @p TRUE.
128 */
129#define CH_CFG_OPTIMIZE_SPEED FALSE
130
131/** @} */
132
133/*===========================================================================*/
134/**
135 * @name Subsystem options
136 * @{
137 */
138/*===========================================================================*/
139
140/**
141 * @brief Time Measurement APIs.
142 * @details If enabled then the time measurement APIs are included in
143 * the kernel.
144 *
145 * @note The default is @p TRUE.
146 */
147#define CH_CFG_USE_TM FALSE
148
149/**
150 * @brief Threads registry APIs.
151 * @details If enabled then the registry APIs are included in the kernel.
152 *
153 * @note The default is @p TRUE.
154 */
155#define CH_CFG_USE_REGISTRY TRUE
156
157/**
158 * @brief Threads synchronization APIs.
159 * @details If enabled then the @p chThdWait() function is included in
160 * the kernel.
161 *
162 * @note The default is @p TRUE.
163 */
164#define CH_CFG_USE_WAITEXIT TRUE
165
166/**
167 * @brief Semaphores APIs.
168 * @details If enabled then the Semaphores APIs are included in the kernel.
169 *
170 * @note The default is @p TRUE.
171 */
172#define CH_CFG_USE_SEMAPHORES TRUE
173
174/**
175 * @brief Semaphores queuing mode.
176 * @details If enabled then the threads are enqueued on semaphores by
177 * priority rather than in FIFO order.
178 *
179 * @note The default is @p FALSE. Enable this if you have special
180 * requirements.
181 * @note Requires @p CH_CFG_USE_SEMAPHORES.
182 */
183#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
184
185/**
186 * @brief Mutexes APIs.
187 * @details If enabled then the mutexes APIs are included in the kernel.
188 *
189 * @note The default is @p TRUE.
190 */
191#define CH_CFG_USE_MUTEXES TRUE
192
193/**
194 * @brief Enables recursive behavior on mutexes.
195 * @note Recursive mutexes are heavier and have an increased
196 * memory footprint.
197 *
198 * @note The default is @p FALSE.
199 * @note Requires @p CH_CFG_USE_MUTEXES.
200 */
201#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
202
203/**
204 * @brief Conditional Variables APIs.
205 * @details If enabled then the conditional variables APIs are included
206 * in the kernel.
207 *
208 * @note The default is @p TRUE.
209 * @note Requires @p CH_CFG_USE_MUTEXES.
210 */
211#define CH_CFG_USE_CONDVARS TRUE
212
213/**
214 * @brief Conditional Variables APIs with timeout.
215 * @details If enabled then the conditional variables APIs with timeout
216 * specification are included in the kernel.
217 *
218 * @note The default is @p TRUE.
219 * @note Requires @p CH_CFG_USE_CONDVARS.
220 */
221#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE
222
223/**
224 * @brief Events Flags APIs.
225 * @details If enabled then the event flags APIs are included in the kernel.
226 *
227 * @note The default is @p TRUE.
228 */
229#define CH_CFG_USE_EVENTS TRUE
230
231/**
232 * @brief Events Flags APIs with timeout.
233 * @details If enabled then the events APIs with timeout specification
234 * are included in the kernel.
235 *
236 * @note The default is @p TRUE.
237 * @note Requires @p CH_CFG_USE_EVENTS.
238 */
239#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
240
241/**
242 * @brief Synchronous Messages APIs.
243 * @details If enabled then the synchronous messages APIs are included
244 * in the kernel.
245 *
246 * @note The default is @p TRUE.
247 */
248#define CH_CFG_USE_MESSAGES TRUE
249
250/**
251 * @brief Synchronous Messages queuing mode.
252 * @details If enabled then messages are served by priority rather than in
253 * FIFO order.
254 *
255 * @note The default is @p FALSE. Enable this if you have special
256 * requirements.
257 * @note Requires @p CH_CFG_USE_MESSAGES.
258 */
259#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
260
261/**
262 * @brief Mailboxes APIs.
263 * @details If enabled then the asynchronous messages (mailboxes) APIs are
264 * included in the kernel.
265 *
266 * @note The default is @p TRUE.
267 * @note Requires @p CH_CFG_USE_SEMAPHORES.
268 */
269#define CH_CFG_USE_MAILBOXES TRUE
270
271/**
272 * @brief Core Memory Manager APIs.
273 * @details If enabled then the core memory manager APIs are included
274 * in the kernel.
275 *
276 * @note The default is @p TRUE.
277 */
278#define CH_CFG_USE_MEMCORE FALSE
279
280/**
281 * @brief Heap Allocator APIs.
282 * @details If enabled then the memory heap allocator APIs are included
283 * in the kernel.
284 *
285 * @note The default is @p TRUE.
286 * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
287 * @p CH_CFG_USE_SEMAPHORES.
288 * @note Mutexes are recommended.
289 */
290#define CH_CFG_USE_HEAP FALSE
291
292/**
293 * @brief Memory Pools Allocator APIs.
294 * @details If enabled then the memory pools allocator APIs are included
295 * in the kernel.
296 *
297 * @note The default is @p TRUE.
298 */
299#define CH_CFG_USE_MEMPOOLS FALSE
300
301/**
302 * @brief Dynamic Threads APIs.
303 * @details If enabled then the dynamic threads creation APIs are included
304 * in the kernel.
305 *
306 * @note The default is @p TRUE.
307 * @note Requires @p CH_CFG_USE_WAITEXIT.
308 * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
309 */
310#define CH_CFG_USE_DYNAMIC FALSE
311
312/** @} */
313
314/*===========================================================================*/
315/**
316 * @name Debug options
317 * @{
318 */
319/*===========================================================================*/
320
321/**
322 * @brief Debug option, kernel statistics.
323 *
324 * @note The default is @p FALSE.
325 */
326#define CH_DBG_STATISTICS FALSE
327
328/**
329 * @brief Debug option, system state check.
330 * @details If enabled the correct call protocol for system APIs is checked
331 * at runtime.
332 *
333 * @note The default is @p FALSE.
334 */
335#define CH_DBG_SYSTEM_STATE_CHECK FALSE
336
337/**
338 * @brief Debug option, parameters checks.
339 * @details If enabled then the checks on the API functions input
340 * parameters are activated.
341 *
342 * @note The default is @p FALSE.
343 */
344#define CH_DBG_ENABLE_CHECKS FALSE
345
346/**
347 * @brief Debug option, consistency checks.
348 * @details If enabled then all the assertions in the kernel code are
349 * activated. This includes consistency checks inside the kernel,
350 * runtime anomalies and port-defined checks.
351 *
352 * @note The default is @p FALSE.
353 */
354#define CH_DBG_ENABLE_ASSERTS FALSE
355
356/**
357 * @brief Debug option, trace buffer.
358 * @details If enabled then the trace buffer is activated.
359 *
360 * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
361 */
362#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
363
364/**
365 * @brief Trace buffer entries.
366 * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
367 * different from @p CH_DBG_TRACE_MASK_DISABLED.
368 */
369#define CH_DBG_TRACE_BUFFER_SIZE 128
370
371/**
372 * @brief Debug option, stack checks.
373 * @details If enabled then a runtime stack check is performed.
374 *
375 * @note The default is @p FALSE.
376 * @note The stack check is performed in a architecture/port dependent way.
377 * It may not be implemented or some ports.
378 * @note The default failure mode is to halt the system with the global
379 * @p panic_msg variable set to @p NULL.
380 */
381#define CH_DBG_ENABLE_STACK_CHECK FALSE
382
383/**
384 * @brief Debug option, stacks initialization.
385 * @details If enabled then the threads working area is filled with a byte
386 * value when a thread is created. This can be useful for the
387 * runtime measurement of the used stack.
388 *
389 * @note The default is @p FALSE.
390 */
391#define CH_DBG_FILL_THREADS FALSE
392
393/**
394 * @brief Debug option, threads profiling.
395 * @details If enabled then a field is added to the @p thread_t structure that
396 * counts the system ticks occurred while executing the thread.
397 *
398 * @note The default is @p FALSE.
399 * @note This debug option is not currently compatible with the
400 * tickless mode.
401 */
402#define CH_DBG_THREADS_PROFILING FALSE
403
404/** @} */
405
406/*===========================================================================*/
407/**
408 * @name Kernel hooks
409 * @{
410 */
411/*===========================================================================*/
412
413/**
414 * @brief Threads descriptor structure extension.
415 * @details User fields added to the end of the @p thread_t structure.
416 */
417#define CH_CFG_THREAD_EXTRA_FIELDS \
418 /* Add threads custom fields here.*/
419
420/**
421 * @brief Threads initialization hook.
422 * @details User initialization code added to the @p chThdInit() API.
423 *
424 * @note It is invoked from within @p chThdInit() and implicitly from all
425 * the threads creation APIs.
426 */
427#define CH_CFG_THREAD_INIT_HOOK(tp) { \
428 /* Add threads initialization code here.*/ \
429}
430
431/**
432 * @brief Threads finalization hook.
433 * @details User finalization code added to the @p chThdExit() API.
434 */
435#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
436 /* Add threads finalization code here.*/ \
437}
438
439/**
440 * @brief Context switch hook.
441 * @details This hook is invoked just before switching between threads.
442 */
443#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
444 /* Context switch code here.*/ \
445}
446
447/**
448 * @brief ISR enter hook.
449 */
450#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
451 /* IRQ prologue code here.*/ \
452}
453
454/**
455 * @brief ISR exit hook.
456 */
457#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
458 /* IRQ epilogue code here.*/ \
459}
460
461/**
462 * @brief Idle thread enter hook.
463 * @note This hook is invoked within a critical zone, no OS functions
464 * should be invoked from here.
465 * @note This macro can be used to activate a power saving mode.
466 */
467#define CH_CFG_IDLE_ENTER_HOOK() { \
468 /* Idle-enter code here.*/ \
469}
470
471/**
472 * @brief Idle thread leave hook.
473 * @note This hook is invoked within a critical zone, no OS functions
474 * should be invoked from here.
475 * @note This macro can be used to deactivate a power saving mode.
476 */
477#define CH_CFG_IDLE_LEAVE_HOOK() { \
478 /* Idle-leave code here.*/ \
479}
480
481/**
482 * @brief Idle Loop hook.
483 * @details This hook is continuously invoked by the idle thread loop.
484 */
485#define CH_CFG_IDLE_LOOP_HOOK() { \
486 /* Idle loop code here.*/ \
487}
488
489/**
490 * @brief System tick event hook.
491 * @details This hook is invoked in the system tick handler immediately
492 * after processing the virtual timers queue.
493 */
494#define CH_CFG_SYSTEM_TICK_HOOK() { \
495 /* System tick event code here.*/ \
496}
497
498/**
499 * @brief System halt hook.
500 * @details This hook is invoked in case to a system halting error before
501 * the system is halted.
502 */
503#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
504 /* System halt code here.*/ \
505}
506
507/**
508 * @brief Trace hook.
509 * @details This hook is invoked each time a new record is written in the
510 * trace buffer.
511 */
512#define CH_CFG_TRACE_HOOK(tep) { \
513 /* Trace code here.*/ \
514}
515
516/** @} */
517
518/*===========================================================================*/
519/* Port-specific settings (override port settings defaulted in chcore.h). */
520/*===========================================================================*/
521
522#endif /* CHCONF_H */
523
524/** @} */
diff --git a/keyboards/cannonkeys/chimera65/chimera65.c b/keyboards/cannonkeys/chimera65/chimera65.c
new file mode 100644
index 000000000..14f170d9c
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/chimera65.c
@@ -0,0 +1 @@
#include "chimera65.h"
diff --git a/keyboards/cannonkeys/chimera65/chimera65.h b/keyboards/cannonkeys/chimera65/chimera65.h
new file mode 100644
index 000000000..81532f3f1
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/chimera65.h
@@ -0,0 +1,17 @@
1#pragma once
2
3#include "quantum.h"
4
5#define LAYOUT_default( \
6 K000, K001, K002, K003, K004, K005, K006, K007, K008, K009, K010, K011, K012, K013, K014, \
7 K100, K101, K102, K103, K104, K105, K106, K107, K108, K109, K110, K111, K112, K113, K115, \
8 K200, K201, K202, K203, K204, K205, K206, K207, K208, K209, K210, K211, K212, K213, K215, \
9 K300, K301, K302, K303, K304, K305, K306, K307, K308, K309, K310, K311, K312, K313, K315, \
10 K400, K401, K402, K406, K409, K410, K411, K412, K413, K415 \
11) { \
12 { K000, K001, K002, K003, K004, K005, K006, K007, K008, K009, K010, K011, K012, K013, K014, KC_NO }, \
13 { K100, K101, K102, K103, K104, K105, K106, K107, K108, K109, K110, K111, K112, K113, KC_NO, K115 }, \
14 { K200, K201, K202, K203, K204, K205, K206, K207, K208, K209, K210, K211, K212, K213, KC_NO, K215 }, \
15 { K300, K301, K302, K303, K304, K305, K306, K307, K308, K309, K310, K311, K312, K313, KC_NO, K315 }, \
16 { K400, K401, K402, KC_NO, KC_NO, KC_NO, K406, KC_NO, KC_NO, K409, K410, K411, K412, K413, KC_NO, K415 } \
17}
diff --git a/keyboards/cannonkeys/chimera65/config.h b/keyboards/cannonkeys/chimera65/config.h
new file mode 100644
index 000000000..ace3565be
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/config.h
@@ -0,0 +1,89 @@
1/*
2Copyright 2015 Jun Wako <wakojun@gmail.com>
3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17
18#pragma once
19
20/* USB Device descriptor parameter */
21#define VENDOR_ID 0xCA04
22#define PRODUCT_ID 0xC024
23#define DEVICE_VER 0x0001
24/* in python2: list(u"whatever".encode('utf-16-le')) */
25/* at most 32 characters or the ugly hack in usb_main.c borks */
26#define MANUFACTURER CannonKeys
27#define PRODUCT Chimera65
28#define DESCRIPTION Chimera65 Keyboard
29
30/* key matrix size */
31#define MATRIX_ROWS 5
32#define MATRIX_COLS 16
33
34#define MATRIX_COL_PINS { B11, B10, B2, B1, A5, A4, A3, A2, A1, F0, C15, C14, A9, A8, A10, B3 }
35#define MATRIX_ROW_PINS { A13, A14, A15, C13, B8 }
36#define DIODE_DIRECTION COL2ROW
37
38#define BACKLIGHT_LEVELS 6
39#define BACKLIGHT_BREATHING
40#define BREATHING_PERIOD 6
41
42/* define if matrix has ghost */
43//#define MATRIX_HAS_GHOST
44
45/* Set 0 if debouncing isn't needed */
46#define DEBOUNCE 5
47
48/* Mechanical locking support. Use KC_LCAP, KC_LNUM or KC_LSCR instead in keymap */
49#define LOCKING_SUPPORT_ENABLE
50/* Locking resynchronize hack */
51#define LOCKING_RESYNC_ENABLE
52
53// EEPROM usage
54// TODO: refactor with new user EEPROM code (coming soon)
55#define EEPROM_MAGIC 0x451F
56#define EEPROM_MAGIC_ADDR 34
57// Bump this every time we change what we store
58// This will automatically reset the EEPROM with defaults
59// and avoid loading invalid data from the EEPROM
60#define EEPROM_VERSION 0x02
61#define EEPROM_VERSION_ADDR 36
62
63
64#define DYNAMIC_KEYMAP_LAYER_COUNT 4
65// Dynamic macro starts after dynamic keymaps (35+(4*5*15*2)) = (35+600) = 635
66// start + layer * rows * col * 2
67#define DYNAMIC_KEYMAP_EEPROM_ADDR 37
68#define EEPROM_CUSTOM_BACKLIGHT 678
69#define DYNAMIC_KEYMAP_MACRO_EEPROM_ADDR 679
70#define DYNAMIC_KEYMAP_MACRO_EEPROM_SIZE 202
71#define DYNAMIC_KEYMAP_MACRO_COUNT 16
72
73/*
74 * Feature disable options
75 * These options are also useful to firmware size reduction.
76 */
77
78/* disable debug print */
79//#define NO_DEBUG
80
81/* disable print */
82//#define NO_PRINT
83
84/* disable action features */
85//#define NO_ACTION_LAYER
86//#define NO_ACTION_TAPPING
87//#define NO_ACTION_ONESHOT
88//#define NO_ACTION_MACRO
89//#define NO_ACTION_FUNCTION
diff --git a/keyboards/cannonkeys/chimera65/halconf.h b/keyboards/cannonkeys/chimera65/halconf.h
new file mode 100644
index 000000000..64cf68298
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/halconf.h
@@ -0,0 +1,354 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file templates/halconf.h
19 * @brief HAL configuration header.
20 * @details HAL configuration file, this file allows to enable or disable the
21 * various device drivers from your application. You may also use
22 * this file in order to override the device drivers default settings.
23 *
24 * @addtogroup HAL_CONF
25 * @{
26 */
27
28#ifndef _HALCONF_H_
29#define _HALCONF_H_
30
31#include "mcuconf.h"
32
33/**
34 * @brief Enables the PAL subsystem.
35 */
36#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
37#define HAL_USE_PAL TRUE
38#endif
39
40/**
41 * @brief Enables the ADC subsystem.
42 */
43#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
44#define HAL_USE_ADC FALSE
45#endif
46
47/**
48 * @brief Enables the CAN subsystem.
49 */
50#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
51#define HAL_USE_CAN FALSE
52#endif
53
54/**
55 * @brief Enables the DAC subsystem.
56 */
57#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
58#define HAL_USE_DAC FALSE
59#endif
60
61/**
62 * @brief Enables the EXT subsystem.
63 */
64#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
65#define HAL_USE_EXT FALSE
66#endif
67
68/**
69 * @brief Enables the GPT subsystem.
70 */
71#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
72#define HAL_USE_GPT FALSE
73#endif
74
75/**
76 * @brief Enables the I2C subsystem.
77 */
78#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
79#define HAL_USE_I2C TRUE
80#endif
81
82/**
83 * @brief Enables the I2S subsystem.
84 */
85#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
86#define HAL_USE_I2S FALSE
87#endif
88
89/**
90 * @brief Enables the ICU subsystem.
91 */
92#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
93#define HAL_USE_ICU FALSE
94#endif
95
96/**
97 * @brief Enables the MAC subsystem.
98 */
99#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
100#define HAL_USE_MAC FALSE
101#endif
102
103/**
104 * @brief Enables the MMC_SPI subsystem.
105 */
106#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
107#define HAL_USE_MMC_SPI FALSE
108#endif
109
110/**
111 * @brief Enables the PWM subsystem.
112 */
113#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
114#define HAL_USE_PWM TRUE
115#endif
116
117/**
118 * @brief Enables the RTC subsystem.
119 */
120#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
121#define HAL_USE_RTC FALSE
122#endif
123
124/**
125 * @brief Enables the SDC subsystem.
126 */
127#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
128#define HAL_USE_SDC FALSE
129#endif
130
131/**
132 * @brief Enables the SERIAL subsystem.
133 */
134#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
135#define HAL_USE_SERIAL FALSE
136#endif
137
138/**
139 * @brief Enables the SERIAL over USB subsystem.
140 */
141#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
142#define HAL_USE_SERIAL_USB FALSE
143#endif
144
145/**
146 * @brief Enables the SPI subsystem.
147 */
148#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
149#define HAL_USE_SPI FALSE
150#endif
151
152/**
153 * @brief Enables the UART subsystem.
154 */
155#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
156#define HAL_USE_UART FALSE
157#endif
158
159/**
160 * @brief Enables the USB subsystem.
161 */
162#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
163#define HAL_USE_USB TRUE
164#endif
165
166/**
167 * @brief Enables the WDG subsystem.
168 */
169#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
170#define HAL_USE_WDG FALSE
171#endif
172
173/*===========================================================================*/
174/* ADC driver related settings. */
175/*===========================================================================*/
176
177/**
178 * @brief Enables synchronous APIs.
179 * @note Disabling this option saves both code and data space.
180 */
181#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
182#define ADC_USE_WAIT TRUE
183#endif
184
185/**
186 * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
187 * @note Disabling this option saves both code and data space.
188 */
189#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
190#define ADC_USE_MUTUAL_EXCLUSION TRUE
191#endif
192
193/*===========================================================================*/
194/* CAN driver related settings. */
195/*===========================================================================*/
196
197/**
198 * @brief Sleep mode related APIs inclusion switch.
199 */
200#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
201#define CAN_USE_SLEEP_MODE TRUE
202#endif
203
204/*===========================================================================*/
205/* I2C driver related settings. */
206/*===========================================================================*/
207
208/**
209 * @brief Enables the mutual exclusion APIs on the I2C bus.
210 */
211#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
212#define I2C_USE_MUTUAL_EXCLUSION TRUE
213#endif
214
215/*===========================================================================*/
216/* MAC driver related settings. */
217/*===========================================================================*/
218
219/**
220 * @brief Enables an event sources for incoming packets.
221 */
222#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
223#define MAC_USE_ZERO_COPY FALSE
224#endif
225
226/**
227 * @brief Enables an event sources for incoming packets.
228 */
229#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
230#define MAC_USE_EVENTS TRUE
231#endif
232
233/*===========================================================================*/
234/* MMC_SPI driver related settings. */
235/*===========================================================================*/
236
237/**
238 * @brief Delays insertions.
239 * @details If enabled this options inserts delays into the MMC waiting
240 * routines releasing some extra CPU time for the threads with
241 * lower priority, this may slow down the driver a bit however.
242 * This option is recommended also if the SPI driver does not
243 * use a DMA channel and heavily loads the CPU.
244 */
245#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
246#define MMC_NICE_WAITING TRUE
247#endif
248
249/*===========================================================================*/
250/* SDC driver related settings. */
251/*===========================================================================*/
252
253/**
254 * @brief Number of initialization attempts before rejecting the card.
255 * @note Attempts are performed at 10mS intervals.
256 */
257#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
258#define SDC_INIT_RETRY 100
259#endif
260
261/**
262 * @brief Include support for MMC cards.
263 * @note MMC support is not yet implemented so this option must be kept
264 * at @p FALSE.
265 */
266#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
267#define SDC_MMC_SUPPORT FALSE
268#endif
269
270/**
271 * @brief Delays insertions.
272 * @details If enabled this options inserts delays into the MMC waiting
273 * routines releasing some extra CPU time for the threads with
274 * lower priority, this may slow down the driver a bit however.
275 */
276#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
277#define SDC_NICE_WAITING TRUE
278#endif
279
280/*===========================================================================*/
281/* SERIAL driver related settings. */
282/*===========================================================================*/
283
284/**
285 * @brief Default bit rate.
286 * @details Configuration parameter, this is the baud rate selected for the
287 * default configuration.
288 */
289#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
290#define SERIAL_DEFAULT_BITRATE 38400
291#endif
292
293/**
294 * @brief Serial buffers size.
295 * @details Configuration parameter, you can change the depth of the queue
296 * buffers depending on the requirements of your application.
297 * @note The default is 64 bytes for both the transmission and receive
298 * buffers.
299 */
300#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
301#define SERIAL_BUFFERS_SIZE 16
302#endif
303
304/*===========================================================================*/
305/* SERIAL_USB driver related setting. */
306/*===========================================================================*/
307
308/**
309 * @brief Serial over USB buffers size.
310 * @details Configuration parameter, the buffer size must be a multiple of
311 * the USB data endpoint maximum packet size.
312 * @note The default is 64 bytes for both the transmission and receive
313 * buffers.
314 */
315#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
316#define SERIAL_USB_BUFFERS_SIZE 1
317#endif
318
319/*===========================================================================*/
320/* SPI driver related settings. */
321/*===========================================================================*/
322
323/**
324 * @brief Enables synchronous APIs.
325 * @note Disabling this option saves both code and data space.
326 */
327#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
328#define SPI_USE_WAIT TRUE
329#endif
330
331/**
332 * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
333 * @note Disabling this option saves both code and data space.
334 */
335#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
336#define SPI_USE_MUTUAL_EXCLUSION TRUE
337#endif
338
339
340/*===========================================================================*/
341/* USB driver related settings. */
342/*===========================================================================*/
343
344/**
345 * @brief Enables synchronous APIs.
346 * @note Disabling this option saves both code and data space.
347 */
348#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
349#define USB_USE_WAIT TRUE
350#endif
351
352#endif /* _HALCONF_H_ */
353
354/** @} */
diff --git a/keyboards/cannonkeys/chimera65/info.json b/keyboards/cannonkeys/chimera65/info.json
new file mode 100644
index 000000000..75a5f293d
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/info.json
@@ -0,0 +1,7 @@
1{
2 "keyboard_name": "Chimera65",
3 "url": "https://cannonkeys.com",
4 "maintainer": "awkannan",
5 "width": 16,
6 "height": 5
7}
diff --git a/keyboards/cannonkeys/chimera65/keymaps/default/keymap.c b/keyboards/cannonkeys/chimera65/keymaps/default/keymap.c
new file mode 100644
index 000000000..a63fcf6f7
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/keymaps/default/keymap.c
@@ -0,0 +1,44 @@
1/*
2Copyright 2012,2013 Jun Wako <wakojun@gmail.com>
3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17#include QMK_KEYBOARD_H
18
19
20// Each layer gets a name for readability, which is then used in the keymap matrix below.
21// The underscores don't mean anything - you can have a layer called STUFF or any other name.
22// Layer names don't all need to be of the same length, obviously, and you can also skip them
23// entirely and just use numbers.
24#define _BASE 0
25#define _FN1 1
26
27const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
28
29 [_BASE] = LAYOUT_default(
30 KC_GESC, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSPC, KC_DEL,
31 KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSLS, KC_DEL,
32 KC_CAPS, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_NUBS, KC_ENT, KC_PGUP,
33 KC_LSFT, KC_NUHS, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_UP, KC_PGDN,
34 KC_LCTL, KC_LGUI, KC_LALT, KC_SPC, KC_RALT, MO(_FN1), KC_RCTL, KC_LEFT, KC_DOWN, KC_RGHT
35 ),
36
37 [_FN1] = LAYOUT_default(
38 KC_GESC, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL, KC_TRNS,
39 KC_TRNS, KC_TRNS, KC_UP, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
40 BL_BRTG, KC_LEFT, KC_DOWN, KC_RGHT, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
41 BL_INC, BL_DEC, BL_TOGG, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
42 KC_GRV, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, RESET, KC_TRNS, KC_TRNS, KC_TRNS
43 )
44};
diff --git a/keyboards/cannonkeys/chimera65/keymaps/via/keymap.c b/keyboards/cannonkeys/chimera65/keymaps/via/keymap.c
new file mode 100644
index 000000000..a63fcf6f7
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/keymaps/via/keymap.c
@@ -0,0 +1,44 @@
1/*
2Copyright 2012,2013 Jun Wako <wakojun@gmail.com>
3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17#include QMK_KEYBOARD_H
18
19
20// Each layer gets a name for readability, which is then used in the keymap matrix below.
21// The underscores don't mean anything - you can have a layer called STUFF or any other name.
22// Layer names don't all need to be of the same length, obviously, and you can also skip them
23// entirely and just use numbers.
24#define _BASE 0
25#define _FN1 1
26
27const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
28
29 [_BASE] = LAYOUT_default(
30 KC_GESC, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSPC, KC_DEL,
31 KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSLS, KC_DEL,
32 KC_CAPS, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_NUBS, KC_ENT, KC_PGUP,
33 KC_LSFT, KC_NUHS, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_UP, KC_PGDN,
34 KC_LCTL, KC_LGUI, KC_LALT, KC_SPC, KC_RALT, MO(_FN1), KC_RCTL, KC_LEFT, KC_DOWN, KC_RGHT
35 ),
36
37 [_FN1] = LAYOUT_default(
38 KC_GESC, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL, KC_TRNS,
39 KC_TRNS, KC_TRNS, KC_UP, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
40 BL_BRTG, KC_LEFT, KC_DOWN, KC_RGHT, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
41 BL_INC, BL_DEC, BL_TOGG, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
42 KC_GRV, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, RESET, KC_TRNS, KC_TRNS, KC_TRNS
43 )
44};
diff --git a/keyboards/cannonkeys/chimera65/keymaps/via/rules.mk b/keyboards/cannonkeys/chimera65/keymaps/via/rules.mk
new file mode 100644
index 000000000..d12497792
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/keymaps/via/rules.mk
@@ -0,0 +1,5 @@
1# rules.mk overrides to enable VIA
2
3RAW_ENABLE = yes
4DYNAMIC_KEYMAP_ENABLE = yes
5
diff --git a/keyboards/cannonkeys/chimera65/mcuconf.h b/keyboards/cannonkeys/chimera65/mcuconf.h
new file mode 100644
index 000000000..048eb4df6
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/mcuconf.h
@@ -0,0 +1,176 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#ifndef _MCUCONF_H_
18#define _MCUCONF_H_
19
20/*
21 * STM32F0xx drivers configuration.
22 * The following settings override the default settings present in
23 * the various device driver implementation headers.
24 * Note that the settings for each driver only have effect if the whole
25 * driver is enabled in halconf.h.
26 *
27 * IRQ priorities:
28 * 3...0 Lowest...Highest.
29 *
30 * DMA priorities:
31 * 0...3 Lowest...Highest.
32 */
33
34#define STM32F0xx_MCUCONF
35// #define STM32F070xB
36
37/*
38 * HAL driver system settings.
39 */
40#define STM32_NO_INIT FALSE
41#define STM32_PVD_ENABLE FALSE
42#define STM32_PLS STM32_PLS_LEV0
43#define STM32_HSI_ENABLED TRUE
44#define STM32_HSI14_ENABLED TRUE
45#define STM32_HSI48_ENABLED FALSE
46#define STM32_LSI_ENABLED TRUE
47#define STM32_HSE_ENABLED FALSE
48#define STM32_LSE_ENABLED FALSE
49#define STM32_SW STM32_SW_PLL
50#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
51#define STM32_PREDIV_VALUE 1
52#define STM32_PLLMUL_VALUE 12
53#define STM32_HPRE STM32_HPRE_DIV1
54#define STM32_PPRE STM32_PPRE_DIV1
55#define STM32_ADCSW STM32_ADCSW_HSI14
56#define STM32_ADCPRE STM32_ADCPRE_DIV4
57#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
58#define STM32_ADCPRE STM32_ADCPRE_DIV4
59#define STM32_ADCSW STM32_ADCSW_HSI14
60#define STM32_USBSW STM32_USBSW_HSI48
61#define STM32_CECSW STM32_CECSW_HSI
62#define STM32_I2C1SW STM32_I2C1SW_HSI
63#define STM32_USART1SW STM32_USART1SW_PCLK
64#define STM32_RTCSEL STM32_RTCSEL_LSI
65
66/*
67 * ADC driver system settings.
68 */
69#define STM32_ADC_USE_ADC1 FALSE
70#define STM32_ADC_ADC1_DMA_PRIORITY 2
71#define STM32_ADC_IRQ_PRIORITY 2
72#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
73
74/*
75 * EXT driver system settings.
76 */
77#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
78#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
79#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
80#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
81#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
82
83/*
84 * GPT driver system settings.
85 */
86#define STM32_GPT_USE_TIM1 FALSE
87#define STM32_GPT_USE_TIM2 FALSE
88#define STM32_GPT_USE_TIM3 FALSE
89#define STM32_GPT_USE_TIM14 FALSE
90#define STM32_GPT_TIM1_IRQ_PRIORITY 2
91#define STM32_GPT_TIM2_IRQ_PRIORITY 2
92#define STM32_GPT_TIM3_IRQ_PRIORITY 2
93#define STM32_GPT_TIM14_IRQ_PRIORITY 2
94
95/*
96 * I2C driver system settings.
97 */
98#define STM32_I2C_USE_I2C1 TRUE
99#define STM32_I2C_USE_I2C2 FALSE
100#define STM32_I2C_BUSY_TIMEOUT 50
101#define STM32_I2C_I2C1_IRQ_PRIORITY 3
102#define STM32_I2C_I2C2_IRQ_PRIORITY 3
103#define STM32_I2C_USE_DMA TRUE
104#define STM32_I2C_I2C1_DMA_PRIORITY 1
105#define STM32_I2C_I2C2_DMA_PRIORITY 1
106#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
107#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
108#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
109
110/*
111 * ICU driver system settings.
112 */
113#define STM32_ICU_USE_TIM1 FALSE
114#define STM32_ICU_USE_TIM2 FALSE
115#define STM32_ICU_USE_TIM3 FALSE
116#define STM32_ICU_TIM1_IRQ_PRIORITY 3
117#define STM32_ICU_TIM2_IRQ_PRIORITY 3
118#define STM32_ICU_TIM3_IRQ_PRIORITY 3
119
120/*
121 * PWM driver system settings.
122 */
123#define STM32_PWM_USE_ADVANCED FALSE
124#define STM32_PWM_USE_TIM1 FALSE
125#define STM32_PWM_USE_TIM2 FALSE
126#define STM32_PWM_USE_TIM3 TRUE
127#define STM32_PWM_TIM1_IRQ_PRIORITY 3
128#define STM32_PWM_TIM2_IRQ_PRIORITY 3
129#define STM32_PWM_TIM3_IRQ_PRIORITY 3
130
131/*
132 * SERIAL driver system settings.
133 */
134#define STM32_SERIAL_USE_USART1 FALSE
135#define STM32_SERIAL_USE_USART2 FALSE
136#define STM32_SERIAL_USART1_PRIORITY 3
137#define STM32_SERIAL_USART2_PRIORITY 3
138
139/*
140 * SPI driver system settings.
141 */
142#define STM32_SPI_USE_SPI1 FALSE
143#define STM32_SPI_USE_SPI2 TRUE
144#define STM32_SPI_SPI1_DMA_PRIORITY 1
145#define STM32_SPI_SPI2_DMA_PRIORITY 1
146#define STM32_SPI_SPI1_IRQ_PRIORITY 2
147#define STM32_SPI_SPI2_IRQ_PRIORITY 2
148#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
149#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
150#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
151
152/*
153 * ST driver system settings.
154 */
155#define STM32_ST_IRQ_PRIORITY 2
156#define STM32_ST_USE_TIMER 2
157
158/*
159 * UART driver system settings.
160 */
161#define STM32_UART_USE_USART1 FALSE
162#define STM32_UART_USE_USART2 FALSE
163#define STM32_UART_USART1_IRQ_PRIORITY 3
164#define STM32_UART_USART2_IRQ_PRIORITY 3
165#define STM32_UART_USART1_DMA_PRIORITY 0
166#define STM32_UART_USART2_DMA_PRIORITY 0
167#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
168
169/*
170 * USB driver system settings.
171 */
172#define STM32_USB_USE_USB1 TRUE
173#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
174#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
175
176#endif /* _MCUCONF_H_ */
diff --git a/keyboards/cannonkeys/chimera65/readme.md b/keyboards/cannonkeys/chimera65/readme.md
new file mode 100644
index 000000000..e612240e4
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/readme.md
@@ -0,0 +1,12 @@
1# Chimera65
2
3Chimera65 Keyboard
4
5Keyboard Maintainer: [Andrew Kannan](https://github.com/awkannan)
6Hardware Supported: STM32F072CBT6
7
8Make example for this keyboard (after setting up your build environment):
9
10 make cannonkeys/chimera65:default
11
12See the [build environment setup](https://docs.qmk.fm/#/getting_started_build_tools) and the [make instructions](https://docs.qmk.fm/#/getting_started_make_guide) for more information. Brand new to QMK? Start with our [Complete Newbs Guide](https://docs.qmk.fm/#/newbs).
diff --git a/keyboards/cannonkeys/chimera65/rules.mk b/keyboards/cannonkeys/chimera65/rules.mk
new file mode 100644
index 000000000..580a7712c
--- /dev/null
+++ b/keyboards/cannonkeys/chimera65/rules.mk
@@ -0,0 +1,57 @@
1# project specific files
2# SRC = ssd1306.c
3## chip/board settings
4# the next two should match the directories in
5# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
6MCU_FAMILY = STM32
7MCU_SERIES = STM32F0xx
8# linker script to use
9# it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
10# or <this_dir>/ld/
11MCU_LDSCRIPT = STM32F072xB
12# startup code to use
13# is should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/
14MCU_STARTUP = stm32f0xx
15# it should exist either in <chibios>/os/hal/boards/
16# or <this_dir>/boards
17BOARD = ST_STM32F072B_DISCOVERY
18# Cortex version
19# Teensy LC is cortex-m0; Teensy 3.x are cortex-m4
20MCU = cortex-m0
21# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
22ARMV = 6
23# If you want to be able to jump to bootloader from firmware on STM32 MCUs,
24# set the correct BOOTLOADER_ADDRESS. Either set it here, or define it in
25# ./bootloader_defs.h or in ./boards/<FOO>/bootloader_defs.h (if you have
26# a custom board definition that you plan to reuse).
27# If you're not setting it here, leave it commented out.
28# It is chip dependent, the correct number can be looked up here (page 175):
29# http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
30# This also requires a patch to chibios:
31# <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
32#STM32_BOOTLOADER_ADDRESS = 0x1FFFC800
33
34# Build Options
35# comment out to disable the options.
36#
37
38# project specific files
39VPATH += keyboards/cannonkeys/stm32f072
40SRC = keyboard.c \
41 led.c
42
43DFU_ARGS = -d 0483:df11 -a 0 -s 0x08000000:leave
44
45#BOOTMAGIC_ENABLE = yes # Virtual DIP switch configuration
46MOUSEKEY_ENABLE = yes # Mouse keys
47EXTRAKEY_ENABLE = yes # Audio control and System control
48CONSOLE_ENABLE = yes # Console for debug
49COMMAND_ENABLE = yes # Commands for debug and configuration
50SLEEP_LED_ENABLE = yes # Breathing sleep LED during USB suspend
51NKRO_ENABLE = yes # USB Nkey Rollover
52CUSTOM_MATRIX = no # Custom matrix file
53# BACKLIGHT_ENABLE = yes # This is broken on 072 for some reason
54RGBLIGHT_ENABLE = no
55
56# RAW_ENABLE = yes
57# DYNAMIC_KEYMAP_ENABLE = yes
diff --git a/keyboards/cannonkeys/stm32f072/keyboard.c b/keyboards/cannonkeys/stm32f072/keyboard.c
index 9520398d0..5a9ccafff 100644
--- a/keyboards/cannonkeys/stm32f072/keyboard.c
+++ b/keyboards/cannonkeys/stm32f072/keyboard.c
@@ -86,10 +86,9 @@ void matrix_init_board(void);
86void matrix_init_kb(void){ 86void matrix_init_kb(void){
87 eeprom_init_kb(); 87 eeprom_init_kb();
88 /* MOSI pin*/ 88 /* MOSI pin*/
89#ifdef RGBLIGHT_ENABLE
89 palSetPadMode(PORT_WS2812, PIN_WS2812, PAL_MODE_ALTERNATE(0)); 90 palSetPadMode(PORT_WS2812, PIN_WS2812, PAL_MODE_ALTERNATE(0));
90 wait_ms(500); 91 wait_ms(500);
91
92#ifdef RGBLIGHT_ENABLE
93 leds_init(); 92 leds_init();
94#endif 93#endif
95 backlight_init_ports(); 94 backlight_init_ports();
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-05 22:40:16 +0000