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authorMichael Pio <mfmayol@up.edu.ph>2019-05-22 01:49:33 +0800
committerDrashna Jaelre <drashna@live.com>2019-05-21 10:49:33 -0700
commit68501261c3a8dbf04a2f1de7ad23640e8074ab87 (patch)
tree65cf2ca0bc35ee473cdb60fbd0cafab60ddb1b82
parent0aece4ddab37e603699cb4ba9e8b72fdaf5a619c (diff)
downloadqmk_firmware-68501261c3a8dbf04a2f1de7ad23640e8074ab87.tar.gz
qmk_firmware-68501261c3a8dbf04a2f1de7ad23640e8074ab87.zip
[Keyboard] Add Ixora keypad (#5931)
* added ixora files * upload ixora * update readme * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/default/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/default/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * update files according to suggestions * removed unused code
Diffstat
-rw-r--r--keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c101
-rw-r--r--keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.h896
-rw-r--r--keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk5
-rw-r--r--keyboards/peiorisboards/ixora/bootloader_defs.h7
-rw-r--r--keyboards/peiorisboards/ixora/chconf.h521
-rw-r--r--keyboards/peiorisboards/ixora/config.h24
-rw-r--r--keyboards/peiorisboards/ixora/halconf.h350
-rw-r--r--keyboards/peiorisboards/ixora/info.json21
-rw-r--r--keyboards/peiorisboards/ixora/ixora.c43
-rw-r--r--keyboards/peiorisboards/ixora/ixora.h40
-rw-r--r--keyboards/peiorisboards/ixora/keymaps/default/keymap.c42
-rw-r--r--keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c26
-rw-r--r--keyboards/peiorisboards/ixora/mcuconf.h168
-rw-r--r--keyboards/peiorisboards/ixora/readme.md22
-rw-r--r--keyboards/peiorisboards/ixora/rules.mk47
15 files changed, 2313 insertions, 0 deletions
diff --git a/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c
new file mode 100644
index 000000000..19adfb933
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c
@@ -0,0 +1,101 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 http://www.apache.org/licenses/LICENSE-2.0
7 Unless required by applicable law or agreed to in writing, software
8 distributed under the License is distributed on an "AS IS" BASIS,
9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 See the License for the specific language governing permissions and
11 limitations under the License.
12*/
13
14#include "hal.h"
15
16#if HAL_USE_PAL || defined(__DOXYGEN__)
17/**
18 * @brief PAL setup.
19 * @details Digital I/O ports static configuration as defined in @p board.h.
20 * This variable is used by the HAL when initializing the PAL driver.
21 */
22const PALConfig pal_default_config = {
23#if STM32_HAS_GPIOA
24 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
25 VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
26#endif
27#if STM32_HAS_GPIOB
28 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
29 VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
30#endif
31#if STM32_HAS_GPIOC
32 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
33 VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
34#endif
35#if STM32_HAS_GPIOD
36 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
37 VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
38#endif
39#if STM32_HAS_GPIOE
40 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
41 VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
42#endif
43#if STM32_HAS_GPIOF
44 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
45 VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
46#endif
47#if STM32_HAS_GPIOG
48 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
49 VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
50#endif
51#if STM32_HAS_GPIOH
52 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
53 VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
54#endif
55#if STM32_HAS_GPIOI
56 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
57 VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
58#endif
59};
60#endif
61
62void enter_bootloader_mode_if_requested(void);
63
64/**
65 * @brief Early initialization code.
66 * @details This initialization must be performed just after stack setup
67 * and before any other initialization.
68 */
69void __early_init(void) {
70 enter_bootloader_mode_if_requested();
71 stm32_clock_init();
72}
73
74#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
75/**
76 * @brief MMC_SPI card detection.
77 */
78bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
79
80 (void)mmcp;
81 /* TODO: Fill the implementation.*/
82 return true;
83}
84
85/**
86 * @brief MMC_SPI card write protection detection.
87 */
88bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
89
90 (void)mmcp;
91 /* TODO: Fill the implementation.*/
92 return false;
93}
94#endif
95
96/**
97 * @brief Board-specific initialization code.
98 * @todo Add your board-specific code, if any.
99 */
100void boardInit(void) {
101}
diff --git a/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.h b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.h
new file mode 100644
index 000000000..ee9d31e04
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.h
@@ -0,0 +1,896 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16#ifndef _BOARD_H
17#define _BOARD_H
18
19/*
20 * Setup for STMicroelectronics STM32 Nucleo32-F042K6 board.
21 */
22
23/*
24 * Board identifier.
25 */
26#define BOARD_GENERIC_STM32_F042X6
27#define BOARD_NAME "Generic STM32F042 PCB"
28
29/*
30 * Board oscillators-related settings.
31 * NOTE: LSE not fitted.
32 * NOTE: HSE not fitted.
33 */
34#if !defined(STM32_LSECLK)
35#define STM32_LSECLK 0U
36#endif
37
38#define STM32_LSEDRV (3U << 3U)
39
40#if !defined(STM32_HSECLK)
41#define STM32_HSECLK 0U
42#endif
43
44/*
45 * MCU type as defined in the ST header.
46 */
47#define STM32F042x6
48
49/*
50 * IO pins assignments.
51 */
52#define GPIOA_PIN0 0U
53#define GPIOA_PIN1 1U
54#define GPIOA_PIN2 2U
55#define GPIOA_PIN3 3U
56#define GPIOA_PIN4 4U
57#define GPIOA_PIN5 5U
58#define GPIOA_PIN6 6U
59#define GPIOA_PIN7 7U
60#define GPIOA_PIN8 8U
61#define GPIOA_PIN9 9U
62#define GPIOA_PIN10 10U
63#define GPIOA_PIN11 11U
64#define GPIOA_PIN12 12U
65#define GPIOA_PIN13 13U
66#define GPIOA_PIN14 14U
67#define GPIOA_PIN15 15U
68
69#define GPIOB_PIN0 0U
70#define GPIOB_PIN1 1U
71#define GPIOB_PIN2 2U
72#define GPIOB_PIN3 3U
73#define GPIOB_PIN4 4U
74#define GPIOB_PIN5 5U
75#define GPIOB_PIN6 6U
76#define GPIOB_PIN7 7U
77#define GPIOB_PIN8 8U
78#define GPIOB_PIN9 9U
79#define GPIOB_PIN10 10U
80#define GPIOB_PIN11 11U
81#define GPIOB_PIN12 12U
82#define GPIOB_PIN13 13U
83#define GPIOB_PIN14 14U
84#define GPIOB_PIN15 15U
85
86#define GPIOC_PIN0 0U
87#define GPIOC_PIN1 1U
88#define GPIOC_PIN2 2U
89#define GPIOC_PIN3 3U
90#define GPIOC_PIN4 4U
91#define GPIOC_PIN5 5U
92#define GPIOC_PIN6 6U
93#define GPIOC_PIN7 7U
94#define GPIOC_PIN8 8U
95#define GPIOC_PIN9 9U
96#define GPIOC_PIN10 10U
97#define GPIOC_PIN11 11U
98#define GPIOC_PIN12 12U
99#define GPIOC_PIN13 13U
100#define GPIOC_PIN14 14U
101#define GPIOC_PIN15 15U
102
103#define GPIOD_PIN0 0U
104#define GPIOD_PIN1 1U
105#define GPIOD_PIN2 2U
106#define GPIOD_PIN3 3U
107#define GPIOD_PIN4 4U
108#define GPIOD_PIN5 5U
109#define GPIOD_PIN6 6U
110#define GPIOD_PIN7 7U
111#define GPIOD_PIN8 8U
112#define GPIOD_PIN9 9U
113#define GPIOD_PIN10 10U
114#define GPIOD_PIN11 11U
115#define GPIOD_PIN12 12U
116#define GPIOD_PIN13 13U
117#define GPIOD_PIN14 14U
118#define GPIOD_PIN15 15U
119
120#define GPIOE_PIN0 0U
121#define GPIOE_PIN1 1U
122#define GPIOE_PIN2 2U
123#define GPIOE_PIN3 3U
124#define GPIOE_PIN4 4U
125#define GPIOE_PIN5 5U
126#define GPIOE_PIN6 6U
127#define GPIOE_PIN7 7U
128#define GPIOE_PIN8 8U
129#define GPIOE_PIN9 9U
130#define GPIOE_PIN10 10U
131#define GPIOE_PIN11 11U
132#define GPIOE_PIN12 12U
133#define GPIOE_PIN13 13U
134#define GPIOE_PIN14 14U
135#define GPIOE_PIN15 15U
136
137#define GPIOF_PIN0 0U
138#define GPIOF_PIN1 1U
139#define GPIOF_PIN2 2U
140#define GPIOF_PIN3 3U
141#define GPIOF_PIN4 4U
142#define GPIOF_PIN5 5U
143#define GPIOF_PIN6 6U
144#define GPIOF_PIN7 7U
145#define GPIOF_PIN8 8U
146#define GPIOF_PIN9 9U
147#define GPIOF_PIN10 10U
148#define GPIOF_PIN11 11U
149#define GPIOF_PIN12 12U
150#define GPIOF_PIN13 13U
151#define GPIOF_PIN14 14U
152#define GPIOF_PIN15 15U
153
154/*
155 * IO lines assignments.
156 */
157
158#define LINE_BOOT0 PAL_LINE(GPIOB, 8U)
159#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
160#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
161
162/*
163 * I/O ports initial setup, this configuration is established soon after reset
164 * in the initialization code.
165 * Please refer to the STM32 Reference Manual for details.
166 */
167#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
168#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
169#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
170#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
171#define PIN_ODR_LOW(n) (0U << (n))
172#define PIN_ODR_HIGH(n) (1U << (n))
173#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
174#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
175#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
176#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
177#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
178#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
179#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
180#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
181#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
182#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
183
184/*
185 * GPIOA setup:
186 *
187 * PA0 - COL5
188 * PA1 - COL4
189 * PA2 - COL3
190 * PA3 - COL2
191 * PA4 - COL1
192 * PA5 - COL0
193 * PA6 - ROW4
194 * PA7 - ROW3
195 * PA8 - NC
196 * PA9 - ROW1
197 * PA10 - ROW0
198 * PA11 - USB_DM
199 * PA12 - USB_DP
200 * PA13 - COL15/SWDIO (for now, COL15)
201 * PA14 - COL14/SWCLK (for now, COL14)
202 * PA15 - COL13
203 */
204#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
205 PIN_MODE_INPUT(GPIOA_PIN1) | \
206 PIN_MODE_INPUT(GPIOA_PIN2) | \
207 PIN_MODE_INPUT(GPIOA_PIN3) | \
208 PIN_MODE_INPUT(GPIOA_PIN4) | \
209 PIN_MODE_INPUT(GPIOA_PIN5) | \
210 PIN_MODE_INPUT(GPIOA_PIN6) | \
211 PIN_MODE_INPUT(GPIOA_PIN7) | \
212 PIN_MODE_INPUT(GPIOA_PIN8) | \
213 PIN_MODE_INPUT(GPIOA_PIN9) | \
214 PIN_MODE_INPUT(GPIOA_PIN10) | \
215 PIN_MODE_INPUT(GPIOA_PIN11) | \
216 PIN_MODE_INPUT(GPIOA_PIN12) | \
217 PIN_MODE_INPUT(GPIOA_PIN13) | \
218 PIN_MODE_INPUT(GPIOA_PIN14) | \
219 PIN_MODE_INPUT(GPIOA_PIN15))
220#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
221 PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
222 PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
223 PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
224 PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
225 PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
226 PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
227 PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
228 PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
229 PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
230 PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
231 PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
232 PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
233 PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \
234 PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \
235 PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
236#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
237 PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
238 PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
239 PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
240 PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
241 PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
242 PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
243 PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
244 PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
245 PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
246 PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
247 PIN_OSPEED_HIGH(GPIOA_PIN11) | \
248 PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \
249 PIN_OSPEED_VERYLOW(GPIOA_PIN13) | \
250 PIN_OSPEED_VERYLOW(GPIOA_PIN14) | \
251 PIN_OSPEED_VERYLOW(GPIOA_PIN15))
252#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
253 PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
254 PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
255 PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
256 PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
257 PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
258 PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
259 PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
260 PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
261 PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
262 PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
263 PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
264 PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
265 PIN_PUPDR_PULLUP(GPIOA_PIN13) | \
266 PIN_PUPDR_PULLUP(GPIOA_PIN14) | \
267 PIN_PUPDR_PULLUP(GPIOA_PIN15))
268#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
269 PIN_ODR_HIGH(GPIOA_PIN1) | \
270 PIN_ODR_HIGH(GPIOA_PIN2) | \
271 PIN_ODR_HIGH(GPIOA_PIN3) | \
272 PIN_ODR_HIGH(GPIOA_PIN4) | \
273 PIN_ODR_HIGH(GPIOA_PIN5) | \
274 PIN_ODR_HIGH(GPIOA_PIN6) | \
275 PIN_ODR_HIGH(GPIOA_PIN7) | \
276 PIN_ODR_HIGH(GPIOA_PIN8) | \
277 PIN_ODR_HIGH(GPIOA_PIN9) | \
278 PIN_ODR_HIGH(GPIOA_PIN10) | \
279 PIN_ODR_HIGH(GPIOA_PIN11) | \
280 PIN_ODR_HIGH(GPIOA_PIN12) | \
281 PIN_ODR_HIGH(GPIOA_PIN13) | \
282 PIN_ODR_HIGH(GPIOA_PIN14) | \
283 PIN_ODR_HIGH(GPIOA_PIN15))
284#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
285 PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
286 PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
287 PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
288 PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
289 PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
290 PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
291 PIN_AFIO_AF(GPIOA_PIN7, 0U))
292#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
293 PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
294 PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
295 PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
296 PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
297 PIN_AFIO_AF(GPIOA_PIN13, 0U) | \
298 PIN_AFIO_AF(GPIOA_PIN14, 0U) | \
299 PIN_AFIO_AF(GPIOA_PIN15, 0U))
300
301/*
302 * GPIOB setup:
303 *
304 * PB0 - ROW2
305 * PB1 - RGB_D
306 * PB2 - PIN2 (input pullup).
307 * PB3 - COL12
308 * PB4 - COL11
309 * PB5 - COL10
310 * PB6 - COL9
311 * PB7 - COL8
312 * PB8 - BOOT0 (set as output for STM32F042)
313 * PB9 - PIN9 (input pullup).
314 * PB10 - PIN10 (input pullup).
315 * PB11 - PIN11 (input pullup).
316 * PB12 - PIN12 (input pullup).
317 * PB13 - PIN13 (input pullup).
318 * PB14 - PIN14 (input pullup).
319 * PB15 - PIN15 (input pullup).
320 */
321#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
322 PIN_MODE_OUTPUT(GPIOB_PIN1) | \
323 PIN_MODE_INPUT(GPIOB_PIN2) | \
324 PIN_MODE_INPUT(GPIOB_PIN3) | \
325 PIN_MODE_INPUT(GPIOB_PIN4) | \
326 PIN_MODE_INPUT(GPIOB_PIN5) | \
327 PIN_MODE_INPUT(GPIOB_PIN6) | \
328 PIN_MODE_INPUT(GPIOB_PIN7) | \
329 PIN_MODE_OUTPUT(GPIOB_PIN8) | \
330 PIN_MODE_INPUT(GPIOB_PIN9) | \
331 PIN_MODE_INPUT(GPIOB_PIN10) | \
332 PIN_MODE_INPUT(GPIOB_PIN11) | \
333 PIN_MODE_INPUT(GPIOB_PIN12) | \
334 PIN_MODE_INPUT(GPIOB_PIN13) | \
335 PIN_MODE_INPUT(GPIOB_PIN14) | \
336 PIN_MODE_INPUT(GPIOB_PIN15))
337#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
338 PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
339 PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
340 PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
341 PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
342 PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
343 PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
344 PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
345 PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
346 PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
347 PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
348 PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
349 PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
350 PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
351 PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
352 PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
353#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
354 PIN_OSPEED_HIGH(GPIOB_PIN1) | \
355 PIN_OSPEED_HIGH(GPIOB_PIN2) | \
356 PIN_OSPEED_VERYLOW(GPIOB_PIN3) | \
357 PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
358 PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
359 PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
360 PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
361 PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
362 PIN_OSPEED_HIGH(GPIOB_PIN9) | \
363 PIN_OSPEED_HIGH(GPIOB_PIN10) | \
364 PIN_OSPEED_HIGH(GPIOB_PIN11) | \
365 PIN_OSPEED_HIGH(GPIOB_PIN12) | \
366 PIN_OSPEED_HIGH(GPIOB_PIN13) | \
367 PIN_OSPEED_HIGH(GPIOB_PIN14) | \
368 PIN_OSPEED_HIGH(GPIOB_PIN15))
369#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
370 PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
371 PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
372 PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
373 PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
374 PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
375 PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
376 PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
377 PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \
378 PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
379 PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
380 PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
381 PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
382 PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
383 PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
384 PIN_PUPDR_PULLUP(GPIOB_PIN15))
385#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
386 PIN_ODR_HIGH(GPIOB_PIN1) | \
387 PIN_ODR_HIGH(GPIOB_PIN2) | \
388 PIN_ODR_HIGH(GPIOB_PIN3) | \
389 PIN_ODR_HIGH(GPIOB_PIN4) | \
390 PIN_ODR_HIGH(GPIOB_PIN5) | \
391 PIN_ODR_HIGH(GPIOB_PIN6) | \
392 PIN_ODR_HIGH(GPIOB_PIN7) | \
393 PIN_ODR_HIGH(GPIOB_PIN8) | \
394 PIN_ODR_HIGH(GPIOB_PIN9) | \
395 PIN_ODR_HIGH(GPIOB_PIN10) | \
396 PIN_ODR_HIGH(GPIOB_PIN11) | \
397 PIN_ODR_HIGH(GPIOB_PIN12) | \
398 PIN_ODR_HIGH(GPIOB_PIN13) | \
399 PIN_ODR_HIGH(GPIOB_PIN14) | \
400 PIN_ODR_HIGH(GPIOB_PIN15))
401#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
402 PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
403 PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
404 PIN_AFIO_AF(GPIOB_PIN3, 0U) | \
405 PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
406 PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
407 PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
408 PIN_AFIO_AF(GPIOB_PIN7, 0U))
409#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
410 PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
411 PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
412 PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
413 PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
414 PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
415 PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
416 PIN_AFIO_AF(GPIOB_PIN15, 0U))
417
418/*
419 * GPIOC setup:
420 *
421 * PC0 - PIN0 (input pullup).
422 * PC1 - PIN1 (input pullup).
423 * PC2 - PIN2 (input pullup).
424 * PC3 - PIN3 (input pullup).
425 * PC4 - PIN4 (input pullup).
426 * PC5 - PIN5 (input pullup).
427 * PC6 - PIN6 (input pullup).
428 * PC7 - PIN7 (input pullup).
429 * PC8 - PIN8 (input pullup).
430 * PC9 - PIN9 (input pullup).
431 * PC10 - PIN10 (input pullup).
432 * PC11 - PIN11 (input pullup).
433 * PC12 - PIN12 (input pullup).
434 * PC13 - PIN13 (input pullup).
435 * PC14 - PIN14 (input pullup).
436 * PC15 - PIN15 (input pullup).
437 */
438#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
439 PIN_MODE_INPUT(GPIOC_PIN1) | \
440 PIN_MODE_INPUT(GPIOC_PIN2) | \
441 PIN_MODE_INPUT(GPIOC_PIN3) | \
442 PIN_MODE_INPUT(GPIOC_PIN4) | \
443 PIN_MODE_INPUT(GPIOC_PIN5) | \
444 PIN_MODE_INPUT(GPIOC_PIN6) | \
445 PIN_MODE_INPUT(GPIOC_PIN7) | \
446 PIN_MODE_INPUT(GPIOC_PIN8) | \
447 PIN_MODE_INPUT(GPIOC_PIN9) | \
448 PIN_MODE_INPUT(GPIOC_PIN10) | \
449 PIN_MODE_INPUT(GPIOC_PIN11) | \
450 PIN_MODE_INPUT(GPIOC_PIN12) | \
451 PIN_MODE_INPUT(GPIOC_PIN13) | \
452 PIN_MODE_INPUT(GPIOC_PIN14) | \
453 PIN_MODE_INPUT(GPIOC_PIN15))
454#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
455 PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
456 PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
457 PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
458 PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
459 PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
460 PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
461 PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
462 PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
463 PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
464 PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
465 PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
466 PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
467 PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
468 PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
469 PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
470#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \
471 PIN_OSPEED_HIGH(GPIOC_PIN1) | \
472 PIN_OSPEED_HIGH(GPIOC_PIN2) | \
473 PIN_OSPEED_HIGH(GPIOC_PIN3) | \
474 PIN_OSPEED_HIGH(GPIOC_PIN4) | \
475 PIN_OSPEED_HIGH(GPIOC_PIN5) | \
476 PIN_OSPEED_HIGH(GPIOC_PIN6) | \
477 PIN_OSPEED_HIGH(GPIOC_PIN7) | \
478 PIN_OSPEED_HIGH(GPIOC_PIN8) | \
479 PIN_OSPEED_HIGH(GPIOC_PIN9) | \
480 PIN_OSPEED_HIGH(GPIOC_PIN10) | \
481 PIN_OSPEED_HIGH(GPIOC_PIN11) | \
482 PIN_OSPEED_HIGH(GPIOC_PIN12) | \
483 PIN_OSPEED_HIGH(GPIOC_PIN13) | \
484 PIN_OSPEED_HIGH(GPIOC_PIN14) | \
485 PIN_OSPEED_HIGH(GPIOC_PIN15))
486#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
487 PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
488 PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
489 PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
490 PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
491 PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
492 PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
493 PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
494 PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
495 PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
496 PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
497 PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
498 PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
499 PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
500 PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
501 PIN_PUPDR_PULLUP(GPIOC_PIN15))
502#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
503 PIN_ODR_HIGH(GPIOC_PIN1) | \
504 PIN_ODR_HIGH(GPIOC_PIN2) | \
505 PIN_ODR_HIGH(GPIOC_PIN3) | \
506 PIN_ODR_HIGH(GPIOC_PIN4) | \
507 PIN_ODR_HIGH(GPIOC_PIN5) | \
508 PIN_ODR_HIGH(GPIOC_PIN6) | \
509 PIN_ODR_HIGH(GPIOC_PIN7) | \
510 PIN_ODR_HIGH(GPIOC_PIN8) | \
511 PIN_ODR_HIGH(GPIOC_PIN9) | \
512 PIN_ODR_HIGH(GPIOC_PIN10) | \
513 PIN_ODR_HIGH(GPIOC_PIN11) | \
514 PIN_ODR_HIGH(GPIOC_PIN12) | \
515 PIN_ODR_HIGH(GPIOC_PIN13) | \
516 PIN_ODR_HIGH(GPIOC_PIN14) | \
517 PIN_ODR_HIGH(GPIOC_PIN15))
518#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
519 PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
520 PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
521 PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
522 PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
523 PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
524 PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
525 PIN_AFIO_AF(GPIOC_PIN7, 0U))
526#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
527 PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
528 PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
529 PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
530 PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
531 PIN_AFIO_AF(GPIOC_PIN13, 0U) | \
532 PIN_AFIO_AF(GPIOC_PIN14, 0U) | \
533 PIN_AFIO_AF(GPIOC_PIN15, 0U))
534
535/*
536 * GPIOD setup:
537 *
538 * PD0 - PIN0 (input pullup).
539 * PD1 - PIN1 (input pullup).
540 * PD2 - PIN2 (input pullup).
541 * PD3 - PIN3 (input pullup).
542 * PD4 - PIN4 (input pullup).
543 * PD5 - PIN5 (input pullup).
544 * PD6 - PIN6 (input pullup).
545 * PD7 - PIN7 (input pullup).
546 * PD8 - PIN8 (input pullup).
547 * PD9 - PIN9 (input pullup).
548 * PD10 - PIN10 (input pullup).
549 * PD11 - PIN11 (input pullup).
550 * PD12 - PIN12 (input pullup).
551 * PD13 - PIN13 (input pullup).
552 * PD14 - PIN14 (input pullup).
553 * PD15 - PIN15 (input pullup).
554 */
555#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
556 PIN_MODE_INPUT(GPIOD_PIN1) | \
557 PIN_MODE_INPUT(GPIOD_PIN2) | \
558 PIN_MODE_INPUT(GPIOD_PIN3) | \
559 PIN_MODE_INPUT(GPIOD_PIN4) | \
560 PIN_MODE_INPUT(GPIOD_PIN5) | \
561 PIN_MODE_INPUT(GPIOD_PIN6) | \
562 PIN_MODE_INPUT(GPIOD_PIN7) | \
563 PIN_MODE_INPUT(GPIOD_PIN8) | \
564 PIN_MODE_INPUT(GPIOD_PIN9) | \
565 PIN_MODE_INPUT(GPIOD_PIN10) | \
566 PIN_MODE_INPUT(GPIOD_PIN11) | \
567 PIN_MODE_INPUT(GPIOD_PIN12) | \
568 PIN_MODE_INPUT(GPIOD_PIN13) | \
569 PIN_MODE_INPUT(GPIOD_PIN14) | \
570 PIN_MODE_INPUT(GPIOD_PIN15))
571#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
572 PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
573 PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
574 PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
575 PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
576 PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
577 PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
578 PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
579 PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
580 PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
581 PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
582 PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
583 PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
584 PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
585 PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
586 PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
587#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
588 PIN_OSPEED_HIGH(GPIOD_PIN1) | \
589 PIN_OSPEED_HIGH(GPIOD_PIN2) | \
590 PIN_OSPEED_HIGH(GPIOD_PIN3) | \
591 PIN_OSPEED_HIGH(GPIOD_PIN4) | \
592 PIN_OSPEED_HIGH(GPIOD_PIN5) | \
593 PIN_OSPEED_HIGH(GPIOD_PIN6) | \
594 PIN_OSPEED_HIGH(GPIOD_PIN7) | \
595 PIN_OSPEED_HIGH(GPIOD_PIN8) | \
596 PIN_OSPEED_HIGH(GPIOD_PIN9) | \
597 PIN_OSPEED_HIGH(GPIOD_PIN10) | \
598 PIN_OSPEED_HIGH(GPIOD_PIN11) | \
599 PIN_OSPEED_HIGH(GPIOD_PIN12) | \
600 PIN_OSPEED_HIGH(GPIOD_PIN13) | \
601 PIN_OSPEED_HIGH(GPIOD_PIN14) | \
602 PIN_OSPEED_HIGH(GPIOD_PIN15))
603#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
604 PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
605 PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
606 PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
607 PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
608 PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
609 PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
610 PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
611 PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
612 PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
613 PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
614 PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
615 PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
616 PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
617 PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
618 PIN_PUPDR_PULLUP(GPIOD_PIN15))
619#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
620 PIN_ODR_HIGH(GPIOD_PIN1) | \
621 PIN_ODR_HIGH(GPIOD_PIN2) | \
622 PIN_ODR_HIGH(GPIOD_PIN3) | \
623 PIN_ODR_HIGH(GPIOD_PIN4) | \
624 PIN_ODR_HIGH(GPIOD_PIN5) | \
625 PIN_ODR_HIGH(GPIOD_PIN6) | \
626 PIN_ODR_HIGH(GPIOD_PIN7) | \
627 PIN_ODR_HIGH(GPIOD_PIN8) | \
628 PIN_ODR_HIGH(GPIOD_PIN9) | \
629 PIN_ODR_HIGH(GPIOD_PIN10) | \
630 PIN_ODR_HIGH(GPIOD_PIN11) | \
631 PIN_ODR_HIGH(GPIOD_PIN12) | \
632 PIN_ODR_HIGH(GPIOD_PIN13) | \
633 PIN_ODR_HIGH(GPIOD_PIN14) | \
634 PIN_ODR_HIGH(GPIOD_PIN15))
635#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
636 PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
637 PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
638 PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
639 PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
640 PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
641 PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
642 PIN_AFIO_AF(GPIOD_PIN7, 0U))
643#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
644 PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
645 PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
646 PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
647 PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
648 PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
649 PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
650 PIN_AFIO_AF(GPIOD_PIN15, 0U))
651
652/*
653 * GPIOE setup:
654 *
655 * PE0 - PIN0 (input pullup).
656 * PE1 - PIN1 (input pullup).
657 * PE2 - PIN2 (input pullup).
658 * PE3 - PIN3 (input pullup).
659 * PE4 - PIN4 (input pullup).
660 * PE5 - PIN5 (input pullup).
661 * PE6 - PIN6 (input pullup).
662 * PE7 - PIN7 (input pullup).
663 * PE8 - PIN8 (input pullup).
664 * PE9 - PIN9 (input pullup).
665 * PE10 - PIN10 (input pullup).
666 * PE11 - PIN11 (input pullup).
667 * PE12 - PIN12 (input pullup).
668 * PE13 - PIN13 (input pullup).
669 * PE14 - PIN14 (input pullup).
670 * PE15 - PIN15 (input pullup).
671 */
672#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
673 PIN_MODE_INPUT(GPIOE_PIN1) | \
674 PIN_MODE_INPUT(GPIOE_PIN2) | \
675 PIN_MODE_INPUT(GPIOE_PIN3) | \
676 PIN_MODE_INPUT(GPIOE_PIN4) | \
677 PIN_MODE_INPUT(GPIOE_PIN5) | \
678 PIN_MODE_INPUT(GPIOE_PIN6) | \
679 PIN_MODE_INPUT(GPIOE_PIN7) | \
680 PIN_MODE_INPUT(GPIOE_PIN8) | \
681 PIN_MODE_INPUT(GPIOE_PIN9) | \
682 PIN_MODE_INPUT(GPIOE_PIN10) | \
683 PIN_MODE_INPUT(GPIOE_PIN11) | \
684 PIN_MODE_INPUT(GPIOE_PIN12) | \
685 PIN_MODE_INPUT(GPIOE_PIN13) | \
686 PIN_MODE_INPUT(GPIOE_PIN14) | \
687 PIN_MODE_INPUT(GPIOE_PIN15))
688#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
689 PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
690 PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
691 PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
692 PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
693 PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
694 PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
695 PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
696 PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
697 PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
698 PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
699 PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
700 PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
701 PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
702 PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
703 PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
704#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
705 PIN_OSPEED_HIGH(GPIOE_PIN1) | \
706 PIN_OSPEED_HIGH(GPIOE_PIN2) | \
707 PIN_OSPEED_HIGH(GPIOE_PIN3) | \
708 PIN_OSPEED_HIGH(GPIOE_PIN4) | \
709 PIN_OSPEED_HIGH(GPIOE_PIN5) | \
710 PIN_OSPEED_HIGH(GPIOE_PIN6) | \
711 PIN_OSPEED_HIGH(GPIOE_PIN7) | \
712 PIN_OSPEED_HIGH(GPIOE_PIN8) | \
713 PIN_OSPEED_HIGH(GPIOE_PIN9) | \
714 PIN_OSPEED_HIGH(GPIOE_PIN10) | \
715 PIN_OSPEED_HIGH(GPIOE_PIN11) | \
716 PIN_OSPEED_HIGH(GPIOE_PIN12) | \
717 PIN_OSPEED_HIGH(GPIOE_PIN13) | \
718 PIN_OSPEED_HIGH(GPIOE_PIN14) | \
719 PIN_OSPEED_HIGH(GPIOE_PIN15))
720#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
721 PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
722 PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
723 PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
724 PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
725 PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
726 PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
727 PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
728 PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
729 PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
730 PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
731 PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
732 PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
733 PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
734 PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
735 PIN_PUPDR_PULLUP(GPIOE_PIN15))
736#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
737 PIN_ODR_HIGH(GPIOE_PIN1) | \
738 PIN_ODR_HIGH(GPIOE_PIN2) | \
739 PIN_ODR_HIGH(GPIOE_PIN3) | \
740 PIN_ODR_HIGH(GPIOE_PIN4) | \
741 PIN_ODR_HIGH(GPIOE_PIN5) | \
742 PIN_ODR_HIGH(GPIOE_PIN6) | \
743 PIN_ODR_HIGH(GPIOE_PIN7) | \
744 PIN_ODR_HIGH(GPIOE_PIN8) | \
745 PIN_ODR_HIGH(GPIOE_PIN9) | \
746 PIN_ODR_HIGH(GPIOE_PIN10) | \
747 PIN_ODR_HIGH(GPIOE_PIN11) | \
748 PIN_ODR_HIGH(GPIOE_PIN12) | \
749 PIN_ODR_HIGH(GPIOE_PIN13) | \
750 PIN_ODR_HIGH(GPIOE_PIN14) | \
751 PIN_ODR_HIGH(GPIOE_PIN15))
752#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
753 PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
754 PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
755 PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
756 PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
757 PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
758 PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
759 PIN_AFIO_AF(GPIOE_PIN7, 0U))
760#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
761 PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
762 PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
763 PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
764 PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
765 PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
766 PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
767 PIN_AFIO_AF(GPIOE_PIN15, 0U))
768
769/*
770 * GPIOF setup:
771 *
772 * PF0 - COL7
773 * PF1 - COL6
774 * PF2 - PIN2 (input pullup).
775 * PF3 - PIN3 (input pullup).
776 * PF4 - PIN4 (input pullup).
777 * PF5 - PIN5 (input pullup).
778 * PF6 - PIN6 (input pullup).
779 * PF7 - PIN7 (input pullup).
780 * PF8 - PIN8 (input pullup).
781 * PF9 - PIN9 (input pullup).
782 * PF10 - PIN10 (input pullup).
783 * PF11 - PIN11 (input pullup).
784 * PF12 - PIN12 (input pullup).
785 * PF13 - PIN13 (input pullup).
786 * PF14 - PIN14 (input pullup).
787 * PF15 - PIN15 (input pullup).
788 */
789#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
790 PIN_MODE_INPUT(GPIOF_PIN1) | \
791 PIN_MODE_INPUT(GPIOF_PIN2) | \
792 PIN_MODE_INPUT(GPIOF_PIN3) | \
793 PIN_MODE_INPUT(GPIOF_PIN4) | \
794 PIN_MODE_INPUT(GPIOF_PIN5) | \
795 PIN_MODE_INPUT(GPIOF_PIN6) | \
796 PIN_MODE_INPUT(GPIOF_PIN7) | \
797 PIN_MODE_INPUT(GPIOF_PIN8) | \
798 PIN_MODE_INPUT(GPIOF_PIN9) | \
799 PIN_MODE_INPUT(GPIOF_PIN10) | \
800 PIN_MODE_INPUT(GPIOF_PIN11) | \
801 PIN_MODE_INPUT(GPIOF_PIN12) | \
802 PIN_MODE_INPUT(GPIOF_PIN13) | \
803 PIN_MODE_INPUT(GPIOF_PIN14) | \
804 PIN_MODE_INPUT(GPIOF_PIN15))
805#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
806 PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
807 PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
808 PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
809 PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
810 PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
811 PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
812 PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
813 PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
814 PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
815 PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
816 PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
817 PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
818 PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
819 PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
820 PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
821#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
822 PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
823 PIN_OSPEED_HIGH(GPIOF_PIN2) | \
824 PIN_OSPEED_HIGH(GPIOF_PIN3) | \
825 PIN_OSPEED_HIGH(GPIOF_PIN4) | \
826 PIN_OSPEED_HIGH(GPIOF_PIN5) | \
827 PIN_OSPEED_HIGH(GPIOF_PIN6) | \
828 PIN_OSPEED_HIGH(GPIOF_PIN7) | \
829 PIN_OSPEED_HIGH(GPIOF_PIN8) | \
830 PIN_OSPEED_HIGH(GPIOF_PIN9) | \
831 PIN_OSPEED_HIGH(GPIOF_PIN10) | \
832 PIN_OSPEED_HIGH(GPIOF_PIN11) | \
833 PIN_OSPEED_HIGH(GPIOF_PIN12) | \
834 PIN_OSPEED_HIGH(GPIOF_PIN13) | \
835 PIN_OSPEED_HIGH(GPIOF_PIN14) | \
836 PIN_OSPEED_HIGH(GPIOF_PIN15))
837#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
838 PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
839 PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
840 PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
841 PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
842 PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
843 PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
844 PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
845 PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
846 PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
847 PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
848 PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
849 PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
850 PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
851 PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
852 PIN_PUPDR_PULLUP(GPIOF_PIN15))
853#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
854 PIN_ODR_HIGH(GPIOF_PIN1) | \
855 PIN_ODR_HIGH(GPIOF_PIN2) | \
856 PIN_ODR_HIGH(GPIOF_PIN3) | \
857 PIN_ODR_HIGH(GPIOF_PIN4) | \
858 PIN_ODR_HIGH(GPIOF_PIN5) | \
859 PIN_ODR_HIGH(GPIOF_PIN6) | \
860 PIN_ODR_HIGH(GPIOF_PIN7) | \
861 PIN_ODR_HIGH(GPIOF_PIN8) | \
862 PIN_ODR_HIGH(GPIOF_PIN9) | \
863 PIN_ODR_HIGH(GPIOF_PIN10) | \
864 PIN_ODR_HIGH(GPIOF_PIN11) | \
865 PIN_ODR_HIGH(GPIOF_PIN12) | \
866 PIN_ODR_HIGH(GPIOF_PIN13) | \
867 PIN_ODR_HIGH(GPIOF_PIN14) | \
868 PIN_ODR_HIGH(GPIOF_PIN15))
869#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
870 PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
871 PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
872 PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
873 PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
874 PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
875 PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
876 PIN_AFIO_AF(GPIOF_PIN7, 0U))
877#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
878 PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
879 PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
880 PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
881 PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
882 PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
883 PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
884 PIN_AFIO_AF(GPIOF_PIN15, 0U))
885
886#if !defined(_FROM_ASM_)
887#ifdef __cplusplus
888extern "C" {
889#endif
890 void boardInit(void);
891#ifdef __cplusplus
892}
893#endif
894#endif /* _FROM_ASM_ */
895
896#endif /* _BOARD_H */
diff --git a/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk
new file mode 100644
index 000000000..bbeb5bbff
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk
@@ -0,0 +1,5 @@
1# List of all the board related files.
2BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6/board.c
3
4# Required include directories
5BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6
diff --git a/keyboards/peiorisboards/ixora/bootloader_defs.h b/keyboards/peiorisboards/ixora/bootloader_defs.h
new file mode 100644
index 000000000..4994be9c2
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/bootloader_defs.h
@@ -0,0 +1,7 @@
1/* Address for jumping to bootloader on STM32 chips. */
2/* It is chip dependent, the correct number can be looked up here:
3 * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
4 * This also requires a patch to chibios:
5 * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
6 */
7#define STM32_BOOTLOADER_ADDRESS 0x1FFFC400 \ No newline at end of file
diff --git a/keyboards/peiorisboards/ixora/chconf.h b/keyboards/peiorisboards/ixora/chconf.h
new file mode 100644
index 000000000..b836a3b99
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/chconf.h
@@ -0,0 +1,521 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 http://www.apache.org/licenses/LICENSE-2.0
7 Unless required by applicable law or agreed to in writing, software
8 distributed under the License is distributed on an "AS IS" BASIS,
9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 See the License for the specific language governing permissions and
11 limitations under the License.
12*/
13
14/**
15 * @file templates/chconf.h
16 * @brief Configuration file template.
17 * @details A copy of this file must be placed in each project directory, it
18 * contains the application specific kernel settings.
19 *
20 * @addtogroup config
21 * @details Kernel related settings and hooks.
22 * @{
23 */
24
25#ifndef CHCONF_H
26#define CHCONF_H
27
28#define _CHIBIOS_RT_CONF_
29
30/*===========================================================================*/
31/**
32 * @name System timers settings
33 * @{
34 */
35/*===========================================================================*/
36
37/**
38 * @brief System time counter resolution.
39 * @note Allowed values are 16 or 32 bits.
40 */
41#define CH_CFG_ST_RESOLUTION 32
42
43/**
44 * @brief System tick frequency.
45 * @details Frequency of the system timer that drives the system ticks. This
46 * setting also defines the system tick time unit.
47 */
48#define CH_CFG_ST_FREQUENCY 10000
49
50/**
51 * @brief Time delta constant for the tick-less mode.
52 * @note If this value is zero then the system uses the classic
53 * periodic tick. This value represents the minimum number
54 * of ticks that is safe to specify in a timeout directive.
55 * The value one is not valid, timeouts are rounded up to
56 * this value.
57 */
58#define CH_CFG_ST_TIMEDELTA 2
59
60/** @} */
61
62/*===========================================================================*/
63/**
64 * @name Kernel parameters and options
65 * @{
66 */
67/*===========================================================================*/
68
69/**
70 * @brief Round robin interval.
71 * @details This constant is the number of system ticks allowed for the
72 * threads before preemption occurs. Setting this value to zero
73 * disables the preemption for threads with equal priority and the
74 * round robin becomes cooperative. Note that higher priority
75 * threads can still preempt, the kernel is always preemptive.
76 * @note Disabling the round robin preemption makes the kernel more compact
77 * and generally faster.
78 * @note The round robin preemption is not supported in tickless mode and
79 * must be set to zero in that case.
80 */
81#define CH_CFG_TIME_QUANTUM 0
82
83/**
84 * @brief Managed RAM size.
85 * @details Size of the RAM area to be managed by the OS. If set to zero
86 * then the whole available RAM is used. The core memory is made
87 * available to the heap allocator and/or can be used directly through
88 * the simplified core memory allocator.
89 *
90 * @note In order to let the OS manage the whole RAM the linker script must
91 * provide the @p __heap_base__ and @p __heap_end__ symbols.
92 * @note Requires @p CH_CFG_USE_MEMCORE.
93 */
94#define CH_CFG_MEMCORE_SIZE 0
95
96/**
97 * @brief Idle thread automatic spawn suppression.
98 * @details When this option is activated the function @p chSysInit()
99 * does not spawn the idle thread. The application @p main()
100 * function becomes the idle thread and must implement an
101 * infinite loop.
102 */
103#define CH_CFG_NO_IDLE_THREAD FALSE
104
105/* Use __WFI in the idle thread for waiting. Does lower the power
106 * consumption. */
107#define CORTEX_ENABLE_WFI_IDLE TRUE
108
109/** @} */
110
111/*===========================================================================*/
112/**
113 * @name Performance options
114 * @{
115 */
116/*===========================================================================*/
117
118/**
119 * @brief OS optimization.
120 * @details If enabled then time efficient rather than space efficient code
121 * is used when two possible implementations exist.
122 *
123 * @note This is not related to the compiler optimization options.
124 * @note The default is @p TRUE.
125 */
126#define CH_CFG_OPTIMIZE_SPEED TRUE
127
128/** @} */
129
130/*===========================================================================*/
131/**
132 * @name Subsystem options
133 * @{
134 */
135/*===========================================================================*/
136
137/**
138 * @brief Time Measurement APIs.
139 * @details If enabled then the time measurement APIs are included in
140 * the kernel.
141 *
142 * @note The default is @p TRUE.
143 */
144#define CH_CFG_USE_TM FALSE
145
146/**
147 * @brief Threads registry APIs.
148 * @details If enabled then the registry APIs are included in the kernel.
149 *
150 * @note The default is @p TRUE.
151 */
152#define CH_CFG_USE_REGISTRY TRUE
153
154/**
155 * @brief Threads synchronization APIs.
156 * @details If enabled then the @p chThdWait() function is included in
157 * the kernel.
158 *
159 * @note The default is @p TRUE.
160 */
161#define CH_CFG_USE_WAITEXIT TRUE
162
163/**
164 * @brief Semaphores APIs.
165 * @details If enabled then the Semaphores APIs are included in the kernel.
166 *
167 * @note The default is @p TRUE.
168 */
169#define CH_CFG_USE_SEMAPHORES TRUE
170
171/**
172 * @brief Semaphores queuing mode.
173 * @details If enabled then the threads are enqueued on semaphores by
174 * priority rather than in FIFO order.
175 *
176 * @note The default is @p FALSE. Enable this if you have special
177 * requirements.
178 * @note Requires @p CH_CFG_USE_SEMAPHORES.
179 */
180#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
181
182/**
183 * @brief Mutexes APIs.
184 * @details If enabled then the mutexes APIs are included in the kernel.
185 *
186 * @note The default is @p TRUE.
187 */
188#define CH_CFG_USE_MUTEXES TRUE
189
190/**
191 * @brief Enables recursive behavior on mutexes.
192 * @note Recursive mutexes are heavier and have an increased
193 * memory footprint.
194 *
195 * @note The default is @p FALSE.
196 * @note Requires @p CH_CFG_USE_MUTEXES.
197 */
198#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
199
200/**
201 * @brief Conditional Variables APIs.
202 * @details If enabled then the conditional variables APIs are included
203 * in the kernel.
204 *
205 * @note The default is @p TRUE.
206 * @note Requires @p CH_CFG_USE_MUTEXES.
207 */
208#define CH_CFG_USE_CONDVARS TRUE
209
210/**
211 * @brief Conditional Variables APIs with timeout.
212 * @details If enabled then the conditional variables APIs with timeout
213 * specification are included in the kernel.
214 *
215 * @note The default is @p TRUE.
216 * @note Requires @p CH_CFG_USE_CONDVARS.
217 */
218#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
219
220/**
221 * @brief Events Flags APIs.
222 * @details If enabled then the event flags APIs are included in the kernel.
223 *
224 * @note The default is @p TRUE.
225 */
226#define CH_CFG_USE_EVENTS TRUE
227
228/**
229 * @brief Events Flags APIs with timeout.
230 * @details If enabled then the events APIs with timeout specification
231 * are included in the kernel.
232 *
233 * @note The default is @p TRUE.
234 * @note Requires @p CH_CFG_USE_EVENTS.
235 */
236#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
237
238/**
239 * @brief Synchronous Messages APIs.
240 * @details If enabled then the synchronous messages APIs are included
241 * in the kernel.
242 *
243 * @note The default is @p TRUE.
244 */
245#define CH_CFG_USE_MESSAGES TRUE
246
247/**
248 * @brief Synchronous Messages queuing mode.
249 * @details If enabled then messages are served by priority rather than in
250 * FIFO order.
251 *
252 * @note The default is @p FALSE. Enable this if you have special
253 * requirements.
254 * @note Requires @p CH_CFG_USE_MESSAGES.
255 */
256#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
257
258/**
259 * @brief Mailboxes APIs.
260 * @details If enabled then the asynchronous messages (mailboxes) APIs are
261 * included in the kernel.
262 *
263 * @note The default is @p TRUE.
264 * @note Requires @p CH_CFG_USE_SEMAPHORES.
265 */
266#define CH_CFG_USE_MAILBOXES TRUE
267
268/**
269 * @brief Core Memory Manager APIs.
270 * @details If enabled then the core memory manager APIs are included
271 * in the kernel.
272 *
273 * @note The default is @p TRUE.
274 */
275#define CH_CFG_USE_MEMCORE TRUE
276
277/**
278 * @brief Heap Allocator APIs.
279 * @details If enabled then the memory heap allocator APIs are included
280 * in the kernel.
281 *
282 * @note The default is @p TRUE.
283 * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
284 * @p CH_CFG_USE_SEMAPHORES.
285 * @note Mutexes are recommended.
286 */
287#define CH_CFG_USE_HEAP TRUE
288
289/**
290 * @brief Memory Pools Allocator APIs.
291 * @details If enabled then the memory pools allocator APIs are included
292 * in the kernel.
293 *
294 * @note The default is @p TRUE.
295 */
296#define CH_CFG_USE_MEMPOOLS TRUE
297
298/**
299 * @brief Dynamic Threads APIs.
300 * @details If enabled then the dynamic threads creation APIs are included
301 * in the kernel.
302 *
303 * @note The default is @p TRUE.
304 * @note Requires @p CH_CFG_USE_WAITEXIT.
305 * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
306 */
307#define CH_CFG_USE_DYNAMIC TRUE
308
309/** @} */
310
311/*===========================================================================*/
312/**
313 * @name Debug options
314 * @{
315 */
316/*===========================================================================*/
317
318/**
319 * @brief Debug option, kernel statistics.
320 *
321 * @note The default is @p FALSE.
322 */
323#define CH_DBG_STATISTICS FALSE
324
325/**
326 * @brief Debug option, system state check.
327 * @details If enabled the correct call protocol for system APIs is checked
328 * at runtime.
329 *
330 * @note The default is @p FALSE.
331 */
332#define CH_DBG_SYSTEM_STATE_CHECK FALSE
333
334/**
335 * @brief Debug option, parameters checks.
336 * @details If enabled then the checks on the API functions input
337 * parameters are activated.
338 *
339 * @note The default is @p FALSE.
340 */
341#define CH_DBG_ENABLE_CHECKS FALSE
342
343/**
344 * @brief Debug option, consistency checks.
345 * @details If enabled then all the assertions in the kernel code are
346 * activated. This includes consistency checks inside the kernel,
347 * runtime anomalies and port-defined checks.
348 *
349 * @note The default is @p FALSE.
350 */
351#define CH_DBG_ENABLE_ASSERTS FALSE
352
353/**
354 * @brief Debug option, trace buffer.
355 * @details If enabled then the trace buffer is activated.
356 *
357 * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
358 */
359#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
360
361/**
362 * @brief Trace buffer entries.
363 * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
364 * different from @p CH_DBG_TRACE_MASK_DISABLED.
365 */
366#define CH_DBG_TRACE_BUFFER_SIZE 128
367
368/**
369 * @brief Debug option, stack checks.
370 * @details If enabled then a runtime stack check is performed.
371 *
372 * @note The default is @p FALSE.
373 * @note The stack check is performed in a architecture/port dependent way.
374 * It may not be implemented or some ports.
375 * @note The default failure mode is to halt the system with the global
376 * @p panic_msg variable set to @p NULL.
377 */
378#define CH_DBG_ENABLE_STACK_CHECK FALSE
379
380/**
381 * @brief Debug option, stacks initialization.
382 * @details If enabled then the threads working area is filled with a byte
383 * value when a thread is created. This can be useful for the
384 * runtime measurement of the used stack.
385 *
386 * @note The default is @p FALSE.
387 */
388#define CH_DBG_FILL_THREADS FALSE
389
390/**
391 * @brief Debug option, threads profiling.
392 * @details If enabled then a field is added to the @p thread_t structure that
393 * counts the system ticks occurred while executing the thread.
394 *
395 * @note The default is @p FALSE.
396 * @note This debug option is not currently compatible with the
397 * tickless mode.
398 */
399#define CH_DBG_THREADS_PROFILING FALSE
400
401/** @} */
402
403/*===========================================================================*/
404/**
405 * @name Kernel hooks
406 * @{
407 */
408/*===========================================================================*/
409
410/**
411 * @brief Threads descriptor structure extension.
412 * @details User fields added to the end of the @p thread_t structure.
413 */
414#define CH_CFG_THREAD_EXTRA_FIELDS \
415 /* Add threads custom fields here.*/
416
417/**
418 * @brief Threads initialization hook.
419 * @details User initialization code added to the @p chThdInit() API.
420 *
421 * @note It is invoked from within @p chThdInit() and implicitly from all
422 * the threads creation APIs.
423 */
424#define CH_CFG_THREAD_INIT_HOOK(tp) { \
425 /* Add threads initialization code here.*/ \
426}
427
428/**
429 * @brief Threads finalization hook.
430 * @details User finalization code added to the @p chThdExit() API.
431 */
432#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
433 /* Add threads finalization code here.*/ \
434}
435
436/**
437 * @brief Context switch hook.
438 * @details This hook is invoked just before switching between threads.
439 */
440#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
441 /* Context switch code here.*/ \
442}
443
444/**
445 * @brief ISR enter hook.
446 */
447#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
448 /* IRQ prologue code here.*/ \
449}
450
451/**
452 * @brief ISR exit hook.
453 */
454#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
455 /* IRQ epilogue code here.*/ \
456}
457
458/**
459 * @brief Idle thread enter hook.
460 * @note This hook is invoked within a critical zone, no OS functions
461 * should be invoked from here.
462 * @note This macro can be used to activate a power saving mode.
463 */
464#define CH_CFG_IDLE_ENTER_HOOK() { \
465 /* Idle-enter code here.*/ \
466}
467
468/**
469 * @brief Idle thread leave hook.
470 * @note This hook is invoked within a critical zone, no OS functions
471 * should be invoked from here.
472 * @note This macro can be used to deactivate a power saving mode.
473 */
474#define CH_CFG_IDLE_LEAVE_HOOK() { \
475 /* Idle-leave code here.*/ \
476}
477
478/**
479 * @brief Idle Loop hook.
480 * @details This hook is continuously invoked by the idle thread loop.
481 */
482#define CH_CFG_IDLE_LOOP_HOOK() { \
483 /* Idle loop code here.*/ \
484}
485
486/**
487 * @brief System tick event hook.
488 * @details This hook is invoked in the system tick handler immediately
489 * after processing the virtual timers queue.
490 */
491#define CH_CFG_SYSTEM_TICK_HOOK() { \
492 /* System tick event code here.*/ \
493}
494
495/**
496 * @brief System halt hook.
497 * @details This hook is invoked in case to a system halting error before
498 * the system is halted.
499 */
500#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
501 /* System halt code here.*/ \
502}
503
504/**
505 * @brief Trace hook.
506 * @details This hook is invoked each time a new record is written in the
507 * trace buffer.
508 */
509#define CH_CFG_TRACE_HOOK(tep) { \
510 /* Trace code here.*/ \
511}
512
513/** @} */
514
515/*===========================================================================*/
516/* Port-specific settings (override port settings defaulted in chcore.h). */
517/*===========================================================================*/
518
519#endif /* CHCONF_H */
520
521/** @} */ \ No newline at end of file
diff --git a/keyboards/peiorisboards/ixora/config.h b/keyboards/peiorisboards/ixora/config.h
new file mode 100644
index 000000000..bf74b13cc
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/config.h
@@ -0,0 +1,24 @@
1#pragma once
2
3#include "config_common.h"
4
5/* USB Device descriptor parameter */
6#define VENDOR_ID 0xFEED
7#define PRODUCT_ID 0x0C61
8#define DEVICE_VER 0x00C6
9#define MANUFACTURER PeiorisBoards
10#define PRODUCT Ixora Rev1
11#define DESCRIPTION 6key Macropad
12
13/* key matrix size */
14#define MATRIX_ROWS 1
15#define MATRIX_COLS 6
16
17#define MATRIX_ROW_PINS { A0 }
18#define MATRIX_COL_PINS { B4, A15, B3, A1, B6, B5 }
19
20/* COL2ROW, ROW2COL, or CUSTOM_MATRIX */
21#define DIODE_DIRECTION COL2ROW
22
23/* Debounce reduces chatter (unintended double-presses) - set 0 if debouncing is not needed */
24#define DEBOUNCE 0
diff --git a/keyboards/peiorisboards/ixora/halconf.h b/keyboards/peiorisboards/ixora/halconf.h
new file mode 100644
index 000000000..bc2b66f2e
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/halconf.h
@@ -0,0 +1,350 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 http://www.apache.org/licenses/LICENSE-2.0
7 Unless required by applicable law or agreed to in writing, software
8 distributed under the License is distributed on an "AS IS" BASIS,
9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 See the License for the specific language governing permissions and
11 limitations under the License.
12*/
13
14/**
15 * @file templates/halconf.h
16 * @brief HAL configuration header.
17 * @details HAL configuration file, this file allows to enable or disable the
18 * various device drivers from your application. You may also use
19 * this file in order to override the device drivers default settings.
20 *
21 * @addtogroup HAL_CONF
22 * @{
23 */
24
25#ifndef _HALCONF_H_
26#define _HALCONF_H_
27
28#include "mcuconf.h"
29
30/**
31 * @brief Enables the PAL subsystem.
32 */
33#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
34#define HAL_USE_PAL TRUE
35#endif
36
37/**
38 * @brief Enables the ADC subsystem.
39 */
40#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
41#define HAL_USE_ADC FALSE
42#endif
43
44/**
45 * @brief Enables the CAN subsystem.
46 */
47#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
48#define HAL_USE_CAN FALSE
49#endif
50
51/**
52 * @brief Enables the DAC subsystem.
53 */
54#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
55#define HAL_USE_DAC FALSE
56#endif
57
58/**
59 * @brief Enables the EXT subsystem.
60 */
61#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
62#define HAL_USE_EXT FALSE
63#endif
64
65/**
66 * @brief Enables the GPT subsystem.
67 */
68#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
69#define HAL_USE_GPT FALSE
70#endif
71
72/**
73 * @brief Enables the I2C subsystem.
74 */
75#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
76#define HAL_USE_I2C FALSE
77#endif
78
79/**
80 * @brief Enables the I2S subsystem.
81 */
82#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
83#define HAL_USE_I2S FALSE
84#endif
85
86/**
87 * @brief Enables the ICU subsystem.
88 */
89#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
90#define HAL_USE_ICU FALSE
91#endif
92
93/**
94 * @brief Enables the MAC subsystem.
95 */
96#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
97#define HAL_USE_MAC FALSE
98#endif
99
100/**
101 * @brief Enables the MMC_SPI subsystem.
102 */
103#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
104#define HAL_USE_MMC_SPI FALSE
105#endif
106
107/**
108 * @brief Enables the PWM subsystem.
109 */
110#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
111#define HAL_USE_PWM FALSE
112#endif
113
114/**
115 * @brief Enables the RTC subsystem.
116 */
117#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
118#define HAL_USE_RTC FALSE
119#endif
120
121/**
122 * @brief Enables the SDC subsystem.
123 */
124#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
125#define HAL_USE_SDC FALSE
126#endif
127
128/**
129 * @brief Enables the SERIAL subsystem.
130 */
131#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
132#define HAL_USE_SERIAL FALSE
133#endif
134
135/**
136 * @brief Enables the SERIAL over USB subsystem.
137 */
138#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
139#define HAL_USE_SERIAL_USB TRUE
140#endif
141
142/**
143 * @brief Enables the SPI subsystem.
144 */
145#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
146#define HAL_USE_SPI FALSE
147#endif
148
149/**
150 * @brief Enables the UART subsystem.
151 */
152#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
153#define HAL_USE_UART FALSE
154#endif
155
156/**
157 * @brief Enables the USB subsystem.
158 */
159#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
160#define HAL_USE_USB TRUE
161#endif
162
163/**
164 * @brief Enables the WDG subsystem.
165 */
166#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
167#define HAL_USE_WDG FALSE
168#endif
169
170/*===========================================================================*/
171/* ADC driver related settings. */
172/*===========================================================================*/
173
174/**
175 * @brief Enables synchronous APIs.
176 * @note Disabling this option saves both code and data space.
177 */
178#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
179#define ADC_USE_WAIT FALSE
180#endif
181
182/**
183 * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
184 * @note Disabling this option saves both code and data space.
185 */
186#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
187#define ADC_USE_MUTUAL_EXCLUSION FALSE
188#endif
189
190/*===========================================================================*/
191/* CAN driver related settings. */
192/*===========================================================================*/
193
194/**
195 * @brief Sleep mode related APIs inclusion switch.
196 */
197#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
198#define CAN_USE_SLEEP_MODE TRUE
199#endif
200
201/*===========================================================================*/
202/* I2C driver related settings. */
203/*===========================================================================*/
204
205/**
206 * @brief Enables the mutual exclusion APIs on the I2C bus.
207 */
208#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
209#define I2C_USE_MUTUAL_EXCLUSION TRUE
210#endif
211
212/*===========================================================================*/
213/* MAC driver related settings. */
214/*===========================================================================*/
215
216/**
217 * @brief Enables an event sources for incoming packets.
218 */
219#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
220#define MAC_USE_ZERO_COPY FALSE
221#endif
222
223/**
224 * @brief Enables an event sources for incoming packets.
225 */
226#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
227#define MAC_USE_EVENTS TRUE
228#endif
229
230/*===========================================================================*/
231/* MMC_SPI driver related settings. */
232/*===========================================================================*/
233
234/**
235 * @brief Delays insertions.
236 * @details If enabled this options inserts delays into the MMC waiting
237 * routines releasing some extra CPU time for the threads with
238 * lower priority, this may slow down the driver a bit however.
239 * This option is recommended also if the SPI driver does not
240 * use a DMA channel and heavily loads the CPU.
241 */
242#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
243#define MMC_NICE_WAITING TRUE
244#endif
245
246/*===========================================================================*/
247/* SDC driver related settings. */
248/*===========================================================================*/
249
250/**
251 * @brief Number of initialization attempts before rejecting the card.
252 * @note Attempts are performed at 10mS intervals.
253 */
254#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
255#define SDC_INIT_RETRY 100
256#endif
257
258/**
259 * @brief Include support for MMC cards.
260 * @note MMC support is not yet implemented so this option must be kept
261 * at @p FALSE.
262 */
263#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
264#define SDC_MMC_SUPPORT FALSE
265#endif
266
267/**
268 * @brief Delays insertions.
269 * @details If enabled this options inserts delays into the MMC waiting
270 * routines releasing some extra CPU time for the threads with
271 * lower priority, this may slow down the driver a bit however.
272 */
273#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
274#define SDC_NICE_WAITING TRUE
275#endif
276
277/*===========================================================================*/
278/* SERIAL driver related settings. */
279/*===========================================================================*/
280
281/**
282 * @brief Default bit rate.
283 * @details Configuration parameter, this is the baud rate selected for the
284 * default configuration.
285 */
286#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
287#define SERIAL_DEFAULT_BITRATE 38400
288#endif
289
290/**
291 * @brief Serial buffers size.
292 * @details Configuration parameter, you can change the depth of the queue
293 * buffers depending on the requirements of your application.
294 * @note The default is 64 bytes for both the transmission and receive
295 * buffers.
296 */
297#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
298#define SERIAL_BUFFERS_SIZE 16
299#endif
300
301/*===========================================================================*/
302/* SERIAL_USB driver related setting. */
303/*===========================================================================*/
304
305/**
306 * @brief Serial over USB buffers size.
307 * @details Configuration parameter, the buffer size must be a multiple of
308 * the USB data endpoint maximum packet size.
309 * @note The default is 64 bytes for both the transmission and receive
310 * buffers.
311 */
312#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
313#define SERIAL_USB_BUFFERS_SIZE 256
314#endif
315
316/*===========================================================================*/
317/* SPI driver related settings. */
318/*===========================================================================*/
319
320/**
321 * @brief Enables synchronous APIs.
322 * @note Disabling this option saves both code and data space.
323 */
324#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
325#define SPI_USE_WAIT FALSE
326#endif
327
328/**
329 * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
330 * @note Disabling this option saves both code and data space.
331 */
332#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
333#define SPI_USE_MUTUAL_EXCLUSION FALSE
334#endif
335
336/*===========================================================================*/
337/* USB driver related settings. */
338/*===========================================================================*/
339
340/**
341 * @brief Enables synchronous APIs.
342 * @note Disabling this option saves both code and data space.
343 */
344#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
345#define USB_USE_WAIT TRUE
346#endif
347
348#endif /* _HALCONF_H_ */
349
350/** @} */ \ No newline at end of file
diff --git a/keyboards/peiorisboards/ixora/info.json b/keyboards/peiorisboards/ixora/info.json
new file mode 100644
index 000000000..a1818632c
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/info.json
@@ -0,0 +1,21 @@
1{
2 "keyboard_name": "Ixora",
3 "url": "",
4 "maintainer": "Peioris",
5 "width": 3,
6 "height": 2,
7 "layouts": {
8 "LAYOUT_full": {
9 "layout": [{"label":"1", "x":0, "y":0}, {"label":"2", "x":1, "y":0}, {"label":"3", "x":2, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}]
10 },
11 "LAYOUT_blocker_right": {
12 "layout": [{"label":"1", "x":0, "y":0}, {"label":"2", "x":1, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}]
13 },
14 "LAYOUT_blocker_left": {
15 "layout": [{"label":"2", "x":1, "y":0}, {"label":"3", "x":2, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}]
16 },
17 "LAYOUT_arrows": {
18 "layout": [{"label":"\u2191", "x":1, "y":0}, {"label":"\u2190", "x":0, "y":1}, {"label":"\u2193", "x":1, "y":1}, {"label":"\u2192", "x":2, "y":1}]
19 }
20 }
21 }
diff --git a/keyboards/peiorisboards/ixora/ixora.c b/keyboards/peiorisboards/ixora/ixora.c
new file mode 100644
index 000000000..7996db629
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/ixora.c
@@ -0,0 +1,43 @@
1#include "ixora.h"
2
3void matrix_init_kb(void) {
4 // put your keyboard start-up code here
5 // runs once when the firmware starts up
6 setPinOutput(A8);
7 setPinOutput(A9);
8 setPinOutput(A10);
9 writePinLow(A8);
10 writePinLow(A9);
11 writePinLow(A10);
12
13 matrix_init_user();
14}
15
16void matrix_scan_kb(void) {
17
18 matrix_scan_user();
19}
20
21bool process_record_kb(uint16_t keycode, keyrecord_t *record) {
22
23 return process_record_user(keycode, record);
24}
25
26void led_set_kb(uint8_t usb_led) {
27 if (IS_LED_ON(usb_led, USB_LED_CAPS_LOCK)) {
28 writePinHigh(A10);
29 } else {
30 writePinLow(A10);
31 }
32 if (IS_LED_ON(usb_led, USB_LED_NUM_LOCK)) {
33 writePinHigh(A9);
34 } else {
35 writePinLow(A9);
36 }
37 if (IS_LED_ON(usb_led, USB_LED_SCROLL_LOCK)) {
38 writePinHigh(A8);
39 } else {
40 writePinLow(A8);
41 }
42 led_set_user(usb_led);
43}
diff --git a/keyboards/peiorisboards/ixora/ixora.h b/keyboards/peiorisboards/ixora/ixora.h
new file mode 100644
index 000000000..92cf6586a
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/ixora.h
@@ -0,0 +1,40 @@
1#pragma once
2
3#define XXX KC_NO
4
5#include "quantum.h"
6
7// This a shortcut to help you visually see your layout.
8
9#define LAYOUT_full( \
10 K00, K01, K02, \
11 K03, K04, K05 \
12) \
13{ \
14 { K00, K01, K02, K03, K04, K05 } \
15}
16
17#define LAYOUT_blocker_right( \
18 K00, K01, \
19 K03, K04, K05 \
20) \
21{ \
22 { K00, K01, XXX, K03, K04, K05 } \
23}
24
25#define LAYOUT_blocker_left( \
26 K01, K02, \
27 K03, K04, K05 \
28) \
29{ \
30 { XXX, K01, K02, K03, K04, K05 } \
31}
32
33#define LAYOUT_arrows( \
34 K01, \
35 K03, K04, K05 \
36) \
37{ \
38 { XXX, K01, XXX, K03, K04, K05 } \
39}
40
diff --git a/keyboards/peiorisboards/ixora/keymaps/default/keymap.c b/keyboards/peiorisboards/ixora/keymaps/default/keymap.c
new file mode 100644
index 000000000..85a646851
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/keymaps/default/keymap.c
@@ -0,0 +1,42 @@
1/* Copyright 2018 Peioris
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include QMK_KEYBOARD_H
18
19const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
20 /* Keymap _BL: (Base Layer) Default Layer
21 * ,-----------------.
22 * |RESET| 2 | 3 |
23 * |-----------------|
24 * |Caps |NmLk |ScLk |
25 * `-----------------'
26 */
27[0] = LAYOUT_full(
28 RESET, KC_2, KC_3,
29 KC_CAPS, KC_NLCK, KC_SLCK)
30};
31
32void matrix_init_user(void) {
33 //user initialization
34}
35
36void matrix_scan_user(void) {
37 //user matrix
38}
39
40bool process_record_user(uint16_t keycode, keyrecord_t *record) {
41 return true;
42}
diff --git a/keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c b/keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c
new file mode 100644
index 000000000..3e08c7801
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c
@@ -0,0 +1,26 @@
1#include QMK_KEYBOARD_H
2
3const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
4 /* Keymap _BL: (Base Layer) Default Layer
5 * ,-----------------.
6 * |RESET| 2 | 3 |
7 * |-----------------|
8 * |Caps |NmLk |ScLk |
9 * `-----------------'
10 */
11[0] = LAYOUT_full(
12 KC_PSCR, KC_MUTE, LGUI(KC_1),
13 KC_MPRV, KC_MPLY, KC_MNXT)
14};
15
16void matrix_init_user(void) {
17 //user initialization
18}
19
20void matrix_scan_user(void) {
21 //user matrix
22}
23
24bool process_record_user(uint16_t keycode, keyrecord_t *record) {
25 return true;
26}
diff --git a/keyboards/peiorisboards/ixora/mcuconf.h b/keyboards/peiorisboards/ixora/mcuconf.h
new file mode 100644
index 000000000..4643e9f92
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/mcuconf.h
@@ -0,0 +1,168 @@
1/*
2 ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 http://www.apache.org/licenses/LICENSE-2.0
7 Unless required by applicable law or agreed to in writing, software
8 distributed under the License is distributed on an "AS IS" BASIS,
9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 See the License for the specific language governing permissions and
11 limitations under the License.
12*/
13
14#ifndef _MCUCONF_H_
15#define _MCUCONF_H_
16
17/*
18 * STM32F0xx drivers configuration.
19 * The following settings override the default settings present in
20 * the various device driver implementation headers.
21 * Note that the settings for each driver only have effect if the whole
22 * driver is enabled in halconf.h.
23 *
24 * IRQ priorities:
25 * 3...0 Lowest...Highest.
26 *
27 * DMA priorities:
28 * 0...3 Lowest...Highest.
29 */
30
31#define STM32F0xx_MCUCONF
32
33/*
34 * HAL driver system settings.
35 */
36#define STM32_NO_INIT FALSE
37#define STM32_PVD_ENABLE FALSE
38#define STM32_PLS STM32_PLS_LEV0
39#define STM32_HSI_ENABLED TRUE
40#define STM32_HSI14_ENABLED TRUE
41#define STM32_HSI48_ENABLED FALSE
42#define STM32_LSI_ENABLED TRUE
43#define STM32_HSE_ENABLED FALSE
44#define STM32_LSE_ENABLED FALSE
45#define STM32_SW STM32_SW_PLL
46#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
47#define STM32_PREDIV_VALUE 1
48#define STM32_PLLMUL_VALUE 12
49#define STM32_HPRE STM32_HPRE_DIV1
50#define STM32_PPRE STM32_PPRE_DIV1
51#define STM32_ADCSW STM32_ADCSW_HSI14
52#define STM32_ADCPRE STM32_ADCPRE_DIV4
53#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
54#define STM32_ADCPRE STM32_ADCPRE_DIV4
55#define STM32_ADCSW STM32_ADCSW_HSI14
56#define STM32_USBSW STM32_USBSW_HSI48
57#define STM32_CECSW STM32_CECSW_HSI
58#define STM32_I2C1SW STM32_I2C1SW_HSI
59#define STM32_USART1SW STM32_USART1SW_PCLK
60#define STM32_RTCSEL STM32_RTCSEL_LSI
61
62/*
63 * ADC driver system settings.
64 */
65#define STM32_ADC_USE_ADC1 FALSE
66#define STM32_ADC_ADC1_DMA_PRIORITY 2
67#define STM32_ADC_IRQ_PRIORITY 2
68#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
69
70/*
71 * EXT driver system settings.
72 */
73#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
74#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
75#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
76#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
77#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
78
79/*
80 * GPT driver system settings.
81 */
82#define STM32_GPT_USE_TIM1 FALSE
83#define STM32_GPT_USE_TIM2 FALSE
84#define STM32_GPT_USE_TIM3 FALSE
85#define STM32_GPT_USE_TIM14 FALSE
86#define STM32_GPT_TIM1_IRQ_PRIORITY 2
87#define STM32_GPT_TIM2_IRQ_PRIORITY 2
88#define STM32_GPT_TIM3_IRQ_PRIORITY 2
89#define STM32_GPT_TIM14_IRQ_PRIORITY 2
90
91/*
92 * I2C driver system settings.
93 */
94#define STM32_I2C_USE_I2C1 FALSE
95#define STM32_I2C_USE_I2C2 FALSE
96#define STM32_I2C_BUSY_TIMEOUT 50
97#define STM32_I2C_I2C1_IRQ_PRIORITY 3
98#define STM32_I2C_I2C2_IRQ_PRIORITY 3
99#define STM32_I2C_USE_DMA TRUE
100#define STM32_I2C_I2C1_DMA_PRIORITY 1
101#define STM32_I2C_I2C2_DMA_PRIORITY 1
102#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
103
104/*
105 * ICU driver system settings.
106 */
107#define STM32_ICU_USE_TIM1 FALSE
108#define STM32_ICU_USE_TIM2 FALSE
109#define STM32_ICU_USE_TIM3 FALSE
110#define STM32_ICU_TIM1_IRQ_PRIORITY 3
111#define STM32_ICU_TIM2_IRQ_PRIORITY 3
112#define STM32_ICU_TIM3_IRQ_PRIORITY 3
113
114/*
115 * PWM driver system settings.
116 */
117#define STM32_PWM_USE_ADVANCED FALSE
118#define STM32_PWM_USE_TIM1 FALSE
119#define STM32_PWM_USE_TIM2 FALSE
120#define STM32_PWM_USE_TIM3 FALSE
121#define STM32_PWM_TIM1_IRQ_PRIORITY 3
122#define STM32_PWM_TIM2_IRQ_PRIORITY 3
123#define STM32_PWM_TIM3_IRQ_PRIORITY 3
124
125/*
126 * SERIAL driver system settings.
127 */
128#define STM32_SERIAL_USE_USART1 FALSE
129#define STM32_SERIAL_USE_USART2 FALSE
130#define STM32_SERIAL_USART1_PRIORITY 3
131#define STM32_SERIAL_USART2_PRIORITY 3
132
133/*
134 * SPI driver system settings.
135 */
136#define STM32_SPI_USE_SPI1 FALSE
137#define STM32_SPI_USE_SPI2 FALSE
138#define STM32_SPI_SPI1_DMA_PRIORITY 1
139#define STM32_SPI_SPI2_DMA_PRIORITY 1
140#define STM32_SPI_SPI1_IRQ_PRIORITY 2
141#define STM32_SPI_SPI2_IRQ_PRIORITY 2
142#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
143
144/*
145 * ST driver system settings.
146 */
147#define STM32_ST_IRQ_PRIORITY 2
148#define STM32_ST_USE_TIMER 2
149
150/*
151 * UART driver system settings.
152 */
153#define STM32_UART_USE_USART1 FALSE
154#define STM32_UART_USE_USART2 FALSE
155#define STM32_UART_USART1_IRQ_PRIORITY 3
156#define STM32_UART_USART2_IRQ_PRIORITY 3
157#define STM32_UART_USART1_DMA_PRIORITY 0
158#define STM32_UART_USART2_DMA_PRIORITY 0
159#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
160
161/*
162 * USB driver system settings.
163 */
164#define STM32_USB_USE_USB1 TRUE
165#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
166#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
167
168#endif /* _MCUCONF_H_ */ \ No newline at end of file
diff --git a/keyboards/peiorisboards/ixora/readme.md b/keyboards/peiorisboards/ixora/readme.md
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index 000000000..1a011ba9a
--- /dev/null
+++ b/keyboards/peiorisboards/ixora/readme.md
@@ -0,0 +1,22 @@
1Ixora
2=========
3
4[Ixora](https://i.imgur.com/GqDk3XY.png)
5
6
7Ixora is an ARM-powered 6-key macropad with a USB connector, hotswap sockets, and indicator LEDs.
8
9Keyboard Maintainer: [Peioris](https://github.com/coarse)
10Hardware Supported: Ixora PCB
11Hardware Availability: [Peioris](https://github.com/coarse)
12
13Make example for this keyboard (after setting up your build environment):
14
15 make peiorisboards/ixora:default:dfu-util
16
17See [build environment setup](https://docs.qmk.fm/build_environment_setup.html) then the [make instructions](https://docs.qmk.fm/make_instructions.html) for more information.
18
19#### Developer's Note
20
21STM32F042xx chips does not allow jumping to bootloader without BOOT0 being set to high, therefore it is impossible to enter the bootloader from sending a `RESET` keycode nor using bootmagic or bootmagic lite.
22The only way to enter bootloader is to hold the BOOT0 button while the keyboard is powering up or after a power reset (done by pressing the reset switch or sending a `RESET` keycode).
diff --git a/keyboards/peiorisboards/ixora/rules.mk b/keyboards/peiorisboards/ixora/rules.mk
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1# project specific files
2
3## chip/board settings
4# - the next two should match the directories in
5# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
6MCU_FAMILY = STM32
7MCU_SERIES = STM32F0xx
8
9# Linker script to use
10# - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
11# or <this_dir>/ld/
12MCU_LDSCRIPT = STM32F042x6
13
14# Startup code to use
15# - it should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/
16MCU_STARTUP = stm32f0xx
17
18# Board: it should exist either in <chibios>/os/hal/boards/
19# or <this_dir>/boards
20BOARD = GENERIC_STM32_F042X6
21
22# Cortex version
23MCU = cortex-m0
24
25# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
26ARMV = 6
27
28# Vector table for application
29# 0x00000000-0x00001000 area is occupied by bootlaoder.*/
30# The CORTEX_VTOR... is needed only for MCHCK/Infinity KB
31#OPT_DEFS = -DCORTEX_VTOR_INIT=0x00001000
32OPT_DEFS =
33
34# Options to pass to dfu-util when flashing
35DFU_ARGS = -d 0483:df11 -a 0 -s 0x08000000:leave
36
37# Build Options
38# comment out to disable the options.
39#
40BACKLIGHT_ENABLE = no
41BOOTMAGIC_ENABLE = yes # Virtual DIP switch configuration
42MOUSEKEY_ENABLE = yes # Mouse keys
43EXTRAKEY_ENABLE = yes # Audio control and System control
44CONSOLE_ENABLE = no # Console for debug
45COMMAND_ENABLE = no # Commands for debug and configuration
46NKRO_ENABLE = yes # USB Nkey Rollover
47NO_USB_STARTUP_CHECK = no # Disable initialization only when usb is plugged in
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 18:40:05 +0000