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| author | Nick Brassel <nick@tzarc.org> | 2021-06-03 09:48:16 +1000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-03 09:48:16 +1000 |
| commit | 597d2e0e7bdc3f2629965a5b393b725e9ab8442b (patch) | |
| tree | e7cabc6c252a4c250704e42f9c2b34da076315b9 /docs/ws2812_driver.md | |
| parent | 35dbe8ba035c8eefc1051226aa8e3dd7cd63a912 (diff) | |
| download | qmk_firmware-597d2e0e7bdc3f2629965a5b393b725e9ab8442b.tar.gz qmk_firmware-597d2e0e7bdc3f2629965a5b393b725e9ab8442b.zip | |
Fix up WS2812 SPI driver on F072. (#13022)
Diffstat (limited to 'docs/ws2812_driver.md')
| -rw-r--r-- | docs/ws2812_driver.md | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/docs/ws2812_driver.md b/docs/ws2812_driver.md index e69400364..101798f21 100644 --- a/docs/ws2812_driver.md +++ b/docs/ws2812_driver.md | |||
| @@ -72,7 +72,9 @@ WS2812_DRIVER = spi | |||
| 72 | Configure the hardware via your config.h: | 72 | Configure the hardware via your config.h: |
| 73 | ```c | 73 | ```c |
| 74 | #define WS2812_SPI SPID1 // default: SPID1 | 74 | #define WS2812_SPI SPID1 // default: SPID1 |
| 75 | #define WS2812_SPI_MOSI_PAL_MODE 5 // Pin "alternate function", see the respective datasheet for the appropriate values for your MCU. default: 5 | 75 | #define WS2812_SPI_MOSI_PAL_MODE 5 // MOSI pin "alternate function", see the respective datasheet for the appropriate values for your MCU. default: 5 |
| 76 | #define WS2812_SPI_SCK_PIN B3 // Required for F072, may be for others -- SCK pin, see the respective datasheet for the appropriate values for your MCU. default: unspecified | ||
| 77 | #define WS2812_SPI_SCK_PAL_MODE 5 // SCK pin "alternate function", see the respective datasheet for the appropriate values for your MCU. default: 5 | ||
| 76 | ``` | 78 | ``` |
| 77 | 79 | ||
| 78 | You must also turn on the SPI feature in your halconf.h and mcuconf.h | 80 | You must also turn on the SPI feature in your halconf.h and mcuconf.h |
| @@ -100,11 +102,11 @@ Only divisors of 2, 4, 8, 16, 32, 64, 128 and 256 are supported by hardware. | |||
| 100 | 102 | ||
| 101 | While not an exhaustive list, the following table provides the scenarios that have been partially validated: | 103 | While not an exhaustive list, the following table provides the scenarios that have been partially validated: |
| 102 | 104 | ||
| 103 | | | SPI1 | SPI2 | SPI3 | | 105 | | | SPI1 | SPI2 | SPI3 | |
| 104 | |-|-|-|-| | 106 | |------|---------------------------------------------|-----------------------------------------|-----------------------| |
| 105 | | f072 | ? | B15 :heavy_check_mark: | N/A | | 107 | | f072 | ? | B15 :heavy_check_mark: (needs SCK: B13) | N/A | |
| 106 | | f103 | A7 :heavy_check_mark: | B15 :heavy_check_mark: | N/A | | 108 | | f103 | A7 :heavy_check_mark: | B15 :heavy_check_mark: | N/A | |
| 107 | | f303 | A7 :heavy_check_mark: B5 :heavy_check_mark: | B15 :heavy_check_mark: | B5 :heavy_check_mark: | | 109 | | f303 | A7 :heavy_check_mark: B5 :heavy_check_mark: | B15 :heavy_check_mark: | B5 :heavy_check_mark: | |
| 108 | 110 | ||
| 109 | *Other supported ChibiOS boards and/or pins may function, it will be highly chip and configuration dependent.* | 111 | *Other supported ChibiOS boards and/or pins may function, it will be highly chip and configuration dependent.* |
| 110 | 112 | ||