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authorskullY <skullydazed@gmail.com>2019-08-30 11:19:03 -0700
committerskullydazed <skullydazed@users.noreply.github.com>2019-08-30 15:01:52 -0700
commitb624f32f944acdc59dcb130674c09090c5c404cb (patch)
treebc13adbba137d122d9a2c2fb2fafcbb08ac10e25 /drivers/arm/i2c_master.h
parent61af76a10d00aba185b8338604171de490a13e3b (diff)
downloadqmk_firmware-b624f32f944acdc59dcb130674c09090c5c404cb.tar.gz
qmk_firmware-b624f32f944acdc59dcb130674c09090c5c404cb.zip
clang-format changes
Diffstat (limited to 'drivers/arm/i2c_master.h')
-rw-r--r--drivers/arm/i2c_master.h91
1 files changed, 45 insertions, 46 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index c8afa31e2..b40fa0a91 100644
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -27,84 +27,83 @@
27#include "ch.h" 27#include "ch.h"
28#include <hal.h> 28#include <hal.h>
29 29
30
31#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx) 30#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
32 #define USE_I2CV1 31# define USE_I2CV1
33#endif 32#endif
34 33
35#ifdef I2C1_BANK 34#ifdef I2C1_BANK
36 #define I2C1_SCL_BANK I2C1_BANK 35# define I2C1_SCL_BANK I2C1_BANK
37 #define I2C1_SDA_BANK I2C1_BANK 36# define I2C1_SDA_BANK I2C1_BANK
38#endif 37#endif
39 38
40#ifndef I2C1_SCL_BANK 39#ifndef I2C1_SCL_BANK
41 #define I2C1_SCL_BANK GPIOB 40# define I2C1_SCL_BANK GPIOB
42#endif 41#endif
43 42
44#ifndef I2C1_SDA_BANK 43#ifndef I2C1_SDA_BANK
45 #define I2C1_SDA_BANK GPIOB 44# define I2C1_SDA_BANK GPIOB
46#endif 45#endif
47 46
48#ifndef I2C1_SCL 47#ifndef I2C1_SCL
49 #define I2C1_SCL 6 48# define I2C1_SCL 6
50#endif 49#endif
51#ifndef I2C1_SDA 50#ifndef I2C1_SDA
52 #define I2C1_SDA 7 51# define I2C1_SDA 7
53#endif 52#endif
54 53
55#ifdef USE_I2CV1 54#ifdef USE_I2CV1
56 #ifndef I2C1_OPMODE 55# ifndef I2C1_OPMODE
57 #define I2C1_OPMODE OPMODE_I2C 56# define I2C1_OPMODE OPMODE_I2C
58 #endif 57# endif
59 #ifndef I2C1_CLOCK_SPEED 58# ifndef I2C1_CLOCK_SPEED
60 #define I2C1_CLOCK_SPEED 100000 /* 400000 */ 59# define I2C1_CLOCK_SPEED 100000 /* 400000 */
61 #endif 60# endif
62 #ifndef I2C1_DUTY_CYCLE 61# ifndef I2C1_DUTY_CYCLE
63 #define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */ 62# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
64 #endif 63# endif
65#else 64#else
66 // The default PAL alternate modes are used to signal that the pins are used for I2C 65// The default PAL alternate modes are used to signal that the pins are used for I2C
67 #ifndef I2C1_SCL_PAL_MODE 66# ifndef I2C1_SCL_PAL_MODE
68 #define I2C1_SCL_PAL_MODE 4 67# define I2C1_SCL_PAL_MODE 4
69 #endif 68# endif
70 #ifndef I2C1_SDA_PAL_MODE 69# ifndef I2C1_SDA_PAL_MODE
71 #define I2C1_SDA_PAL_MODE 4 70# define I2C1_SDA_PAL_MODE 4
72 #endif 71# endif
73 72
74 // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock 73// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
75 // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html 74// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
76 #ifndef I2C1_TIMINGR_PRESC 75# ifndef I2C1_TIMINGR_PRESC
77 #define I2C1_TIMINGR_PRESC 15U 76# define I2C1_TIMINGR_PRESC 15U
78 #endif 77# endif
79 #ifndef I2C1_TIMINGR_SCLDEL 78# ifndef I2C1_TIMINGR_SCLDEL
80 #define I2C1_TIMINGR_SCLDEL 4U 79# define I2C1_TIMINGR_SCLDEL 4U
81 #endif 80# endif
82 #ifndef I2C1_TIMINGR_SDADEL 81# ifndef I2C1_TIMINGR_SDADEL
83 #define I2C1_TIMINGR_SDADEL 2U 82# define I2C1_TIMINGR_SDADEL 2U
84 #endif 83# endif
85 #ifndef I2C1_TIMINGR_SCLH 84# ifndef I2C1_TIMINGR_SCLH
86 #define I2C1_TIMINGR_SCLH 15U 85# define I2C1_TIMINGR_SCLH 15U
87 #endif 86# endif
88 #ifndef I2C1_TIMINGR_SCLL 87# ifndef I2C1_TIMINGR_SCLL
89 #define I2C1_TIMINGR_SCLL 21U 88# define I2C1_TIMINGR_SCLL 21U
90 #endif 89# endif
91#endif 90#endif
92 91
93#ifndef I2C_DRIVER 92#ifndef I2C_DRIVER
94 #define I2C_DRIVER I2CD1 93# define I2C_DRIVER I2CD1
95#endif 94#endif
96 95
97typedef int16_t i2c_status_t; 96typedef int16_t i2c_status_t;
98 97
99#define I2C_STATUS_SUCCESS (0) 98#define I2C_STATUS_SUCCESS (0)
100#define I2C_STATUS_ERROR (-1) 99#define I2C_STATUS_ERROR (-1)
101#define I2C_STATUS_TIMEOUT (-2) 100#define I2C_STATUS_TIMEOUT (-2)
102 101
103void i2c_init(void); 102void i2c_init(void);
104i2c_status_t i2c_start(uint8_t address); 103i2c_status_t i2c_start(uint8_t address);
105i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout); 104i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
106i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout); 105i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
107i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t * tx_body, uint16_t tx_length, uint8_t * rx_body, uint16_t rx_length); 106i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t* tx_body, uint16_t tx_length, uint8_t* rx_body, uint16_t rx_length);
108i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout); 107i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
109i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout); 108i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
110void i2c_stop(void); 109void i2c_stop(void);