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| author | Joel Challis <git@zvecr.com> | 2021-11-01 19:18:33 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-01 19:18:33 +0000 |
| commit | 92385e30cdad61ddfc0461b1ce1340bcb494a68a (patch) | |
| tree | d472f93ed9f4e42e4972630d8178a387b91a51bc /tmk_core | |
| parent | ee371c1295f00c119dd5a1bb2f3d4acedff832a7 (diff) | |
| download | qmk_firmware-92385e30cdad61ddfc0461b1ce1340bcb494a68a.tar.gz qmk_firmware-92385e30cdad61ddfc0461b1ce1340bcb494a68a.zip | |
Manually format develop (#15003)
Diffstat (limited to 'tmk_core')
| -rw-r--r-- | tmk_core/common/chibios/sleep_led.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tmk_core/common/chibios/sleep_led.c b/tmk_core/common/chibios/sleep_led.c index 1c65016a4..477056a45 100644 --- a/tmk_core/common/chibios/sleep_led.c +++ b/tmk_core/common/chibios/sleep_led.c | |||
| @@ -65,7 +65,7 @@ void sleep_led_timer_callback(void) { | |||
| 65 | 65 | ||
| 66 | /* LPTMR clock options */ | 66 | /* LPTMR clock options */ |
| 67 | # define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */ | 67 | # define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */ |
| 68 | # define LPTMR_CLOCK_LPO 1 /* 1kHz clock */ | 68 | # define LPTMR_CLOCK_LPO 1 /* 1kHz clock */ |
| 69 | # define LPTMR_CLOCK_ERCLK32K 2 /* external 32kHz crystal */ | 69 | # define LPTMR_CLOCK_ERCLK32K 2 /* external 32kHz crystal */ |
| 70 | # define LPTMR_CLOCK_OSCERCLK 3 /* output from OSC */ | 70 | # define LPTMR_CLOCK_OSCERCLK 3 /* output from OSC */ |
| 71 | 71 | ||
| @@ -121,7 +121,7 @@ void sleep_led_init(void) { | |||
| 121 | MCG->C2 |= MCG_C2_IRCS; // fast (4MHz) internal ref clock | 121 | MCG->C2 |= MCG_C2_IRCS; // fast (4MHz) internal ref clock |
| 122 | # if defined(KL27) // divide the 8MHz IRC by 2, to have the same MCGIRCLK speed as others | 122 | # if defined(KL27) // divide the 8MHz IRC by 2, to have the same MCGIRCLK speed as others |
| 123 | MCG->MC |= MCG_MC_LIRC_DIV2_DIV2; | 123 | MCG->MC |= MCG_MC_LIRC_DIV2_DIV2; |
| 124 | # endif /* KL27 */ | 124 | # endif /* KL27 */ |
| 125 | MCG->C1 |= MCG_C1_IRCLKEN; // enable internal ref clock | 125 | MCG->C1 |= MCG_C1_IRCLKEN; // enable internal ref clock |
| 126 | // to work in stop mode, also MCG_C1_IREFSTEN | 126 | // to work in stop mode, also MCG_C1_IREFSTEN |
| 127 | // Divide 4MHz by 2^N (N=6) => 62500 irqs/sec => | 127 | // Divide 4MHz by 2^N (N=6) => 62500 irqs/sec => |