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path: root/drivers/avr/i2c_slave.c
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Diffstat (limited to 'drivers/avr/i2c_slave.c')
-rwxr-xr-xdrivers/avr/i2c_slave.c25
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/avr/i2c_slave.c b/drivers/avr/i2c_slave.c
index 27696ca01..18a29a45a 100755
--- a/drivers/avr/i2c_slave.c
+++ b/drivers/avr/i2c_slave.c
@@ -9,23 +9,26 @@
9 9
10#include "i2c_slave.h" 10#include "i2c_slave.h"
11 11
12void i2c_init(uint8_t address){ 12volatile uint8_t i2c_slave_reg[I2C_SLAVE_REG_COUNT];
13
14static volatile uint8_t buffer_address;
15static volatile bool slave_has_register_set = false;
16
17void i2c_slave_init(uint8_t address){
13 // load address into TWI address register 18 // load address into TWI address register
14 TWAR = (address << 1); 19 TWAR = (address << 1);
15 // set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt 20 // set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
16 TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN); 21 TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN);
17} 22}
18 23
19void i2c_stop(void){ 24void i2c_slave_stop(void){
20 // clear acknowledge and enable bits 25 // clear acknowledge and enable bits
21 TWCR &= ~((1 << TWEA) | (1 << TWEN)); 26 TWCR &= ~((1 << TWEA) | (1 << TWEN));
22} 27}
23 28
24ISR(TWI_vect){ 29ISR(TWI_vect){
25 uint8_t ack = 1; 30 uint8_t ack = 1;
26 // temporary stores the received data 31
27 //uint8_t data;
28
29 switch(TW_STATUS){ 32 switch(TW_STATUS){
30 case TW_SR_SLA_ACK: 33 case TW_SR_SLA_ACK:
31 // The device is now a slave receiver 34 // The device is now a slave receiver
@@ -38,13 +41,13 @@ ISR(TWI_vect){
38 if(!slave_has_register_set){ 41 if(!slave_has_register_set){
39 buffer_address = TWDR; 42 buffer_address = TWDR;
40 43
41 if (buffer_address >= RX_BUFFER_SIZE){ // address out of bounds dont ack 44 if (buffer_address >= I2C_SLAVE_REG_COUNT) { // address out of bounds dont ack
42 ack = 0; 45 ack = 0;
43 buffer_address = 0; 46 buffer_address = 0;
44 } 47 }
45 slave_has_register_set = true; // address has been receaved now fill in buffer 48 slave_has_register_set = true; // address has been receaved now fill in buffer
46 } else { 49 } else {
47 rxbuffer[buffer_address] = TWDR; 50 i2c_slave_reg[buffer_address] = TWDR;
48 buffer_address++; 51 buffer_address++;
49 } 52 }
50 break; 53 break;
@@ -52,7 +55,7 @@ ISR(TWI_vect){
52 case TW_ST_SLA_ACK: 55 case TW_ST_SLA_ACK:
53 case TW_ST_DATA_ACK: 56 case TW_ST_DATA_ACK:
54 // This device is a slave transmitter and master has requested data 57 // This device is a slave transmitter and master has requested data
55 TWDR = txbuffer[buffer_address]; 58 TWDR = i2c_slave_reg[buffer_address];
56 buffer_address++; 59 buffer_address++;
57 break; 60 break;
58 61
@@ -63,6 +66,6 @@ ISR(TWI_vect){
63 break; 66 break;
64 } 67 }
65 68
66 // Reset i2c state mahcine to be ready for next interrupt 69 // Reset i2c state machine to be ready for next interrupt
67 TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN); 70 TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN);
68} \ No newline at end of file 71} \ No newline at end of file