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Diffstat (limited to 'keyboards/converter/xt_usb/config.h')
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1/*
2Copyright 2012 Jun Wako <wakojun@gmail.com>
3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17
18#pragma once
19
20#define VENDOR_ID 0xFEED
21#define PRODUCT_ID 0x6512
22#define DEVICE_VER 0x0001
23#define MANUFACTURER QMK
24#define PRODUCT XT keyboard converter
25#define DESCRIPTION convert XT keyboard to USB
26
27
28/* matrix size */
29#define MATRIX_ROWS 16 // keycode bit: 3-0
30#define MATRIX_COLS 8 // keycode bit: 6-4
31
32/* key combination for command */
33#define IS_COMMAND() ( \
34 keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) || \
35 keyboard_report->mods == (MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RSHIFT)) \
36)
37
38
39//#define NO_SUSPEND_POWER_DOWN
40
41/*
42 * XT Pin interrupt
43 */
44#define XT_CLOCK_PORT PORTD
45#define XT_CLOCK_PIN PIND
46#define XT_CLOCK_DDR DDRD
47#define XT_CLOCK_BIT 1
48#define XT_DATA_PORT PORTD
49#define XT_DATA_PIN PIND
50#define XT_DATA_DDR DDRD
51#define XT_DATA_BIT 0
52#define XT_RST_PORT PORTB
53#define XT_RST_PIN PINB
54#define XT_RST_DDR DDRB
55#define XT_RST_BIT 7
56
57/* hard reset: low pulse for 500ms and after that HiZ for safety */
58#define XT_RESET() do { \
59 XT_RST_PORT &= ~(1<<XT_RST_BIT); \
60 XT_RST_DDR |= (1<<XT_RST_BIT); \
61 _delay_ms(500); \
62 XT_RST_DDR &= ~(1<<XT_RST_BIT); \
63} while (0)
64
65/* INT1 for falling edge of clock line */
66#define XT_INT_INIT() do { \
67 EICRA |= ((1<<ISC11) | \
68 (0<<ISC10)); \
69} while (0)
70/* clears flag and enables interrupt */
71#define XT_INT_ON() do { \
72 EIFR |= (1<<INTF1); \
73 EIMSK |= (1<<INT1); \
74} while (0)
75#define XT_INT_OFF() do { \
76 EIMSK &= ~(1<<INT1); \
77} while (0)
78#define XT_INT_VECT INT1_vect