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-rw-r--r--platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld89
-rw-r--r--platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld89
-rw-r--r--platforms/chibios/GENERIC_STM32_F446XE/board/board.mk9
-rw-r--r--platforms/chibios/GENERIC_STM32_F446XE/configs/board.h24
-rw-r--r--platforms/chibios/GENERIC_STM32_F446XE/configs/config.h23
-rw-r--r--platforms/chibios/GENERIC_STM32_F446XE/configs/mcuconf.h361
-rw-r--r--platforms/chibios/GENERIC_STM32_L433XC/board/board.mk9
-rw-r--r--platforms/chibios/GENERIC_STM32_L433XC/configs/board.h24
-rw-r--r--platforms/chibios/GENERIC_STM32_L433XC/configs/config.h26
-rw-r--r--platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h292
-rw-r--r--platforms/chibios/QMK_PROTON_C/convert_to_proton_c.mk7
11 files changed, 948 insertions, 5 deletions
diff --git a/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld b/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld
new file mode 100644
index 000000000..82253d3de
--- /dev/null
+++ b/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld
@@ -0,0 +1,89 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * STM32F411xC memory setup.
19 */
20MEMORY
21{
22 flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
23 flash1 (rx) : org = 0x00000000, len = 0
24 flash2 (rx) : org = 0x00000000, len = 0
25 flash3 (rx) : org = 0x00000000, len = 0
26 flash4 (rx) : org = 0x00000000, len = 0
27 flash5 (rx) : org = 0x00000000, len = 0
28 flash6 (rx) : org = 0x00000000, len = 0
29 flash7 (rx) : org = 0x00000000, len = 0
30 ram0 (wx) : org = 0x20000000, len = 128k
31 ram1 (wx) : org = 0x00000000, len = 0
32 ram2 (wx) : org = 0x00000000, len = 0
33 ram3 (wx) : org = 0x00000000, len = 0
34 ram4 (wx) : org = 0x00000000, len = 0
35 ram5 (wx) : org = 0x00000000, len = 0
36 ram6 (wx) : org = 0x00000000, len = 0
37 ram7 (wx) : org = 0x00000000, len = 0
38}
39
40/* For each data/text section two region are defined, a virtual region
41 and a load region (_LMA suffix).*/
42
43/* Flash region to be used for exception vectors.*/
44REGION_ALIAS("VECTORS_FLASH", flash0);
45REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
46
47/* Flash region to be used for constructors and destructors.*/
48REGION_ALIAS("XTORS_FLASH", flash0);
49REGION_ALIAS("XTORS_FLASH_LMA", flash0);
50
51/* Flash region to be used for code text.*/
52REGION_ALIAS("TEXT_FLASH", flash0);
53REGION_ALIAS("TEXT_FLASH_LMA", flash0);
54
55/* Flash region to be used for read only data.*/
56REGION_ALIAS("RODATA_FLASH", flash0);
57REGION_ALIAS("RODATA_FLASH_LMA", flash0);
58
59/* Flash region to be used for various.*/
60REGION_ALIAS("VARIOUS_FLASH", flash0);
61REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
62
63/* Flash region to be used for RAM(n) initialization data.*/
64REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
65
66/* RAM region to be used for Main stack. This stack accommodates the processing
67 of all exceptions and interrupts.*/
68REGION_ALIAS("MAIN_STACK_RAM", ram0);
69
70/* RAM region to be used for the process stack. This is the stack used by
71 the main() function.*/
72REGION_ALIAS("PROCESS_STACK_RAM", ram0);
73
74/* RAM region to be used for data segment.*/
75REGION_ALIAS("DATA_RAM", ram0);
76REGION_ALIAS("DATA_RAM_LMA", flash0);
77
78/* RAM region to be used for BSS segment.*/
79REGION_ALIAS("BSS_RAM", ram0);
80
81/* RAM region to be used for the default heap.*/
82REGION_ALIAS("HEAP_RAM", ram0);
83
84/* Generic rules inclusion.*/
85INCLUDE rules.ld
86
87/* TinyUF2 bootloader reset support */
88_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
89
diff --git a/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld b/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld
new file mode 100644
index 000000000..1656c67bf
--- /dev/null
+++ b/platforms/chibios/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld
@@ -0,0 +1,89 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * STM32F411xE memory setup.
19 */
20MEMORY
21{
22 flash0 (rx) : org = 0x08000000 + 64k, len = 512k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
23 flash1 (rx) : org = 0x00000000, len = 0
24 flash2 (rx) : org = 0x00000000, len = 0
25 flash3 (rx) : org = 0x00000000, len = 0
26 flash4 (rx) : org = 0x00000000, len = 0
27 flash5 (rx) : org = 0x00000000, len = 0
28 flash6 (rx) : org = 0x00000000, len = 0
29 flash7 (rx) : org = 0x00000000, len = 0
30 ram0 (wx) : org = 0x20000000, len = 128k
31 ram1 (wx) : org = 0x00000000, len = 0
32 ram2 (wx) : org = 0x00000000, len = 0
33 ram3 (wx) : org = 0x00000000, len = 0
34 ram4 (wx) : org = 0x00000000, len = 0
35 ram5 (wx) : org = 0x00000000, len = 0
36 ram6 (wx) : org = 0x00000000, len = 0
37 ram7 (wx) : org = 0x00000000, len = 0
38}
39
40/* For each data/text section two region are defined, a virtual region
41 and a load region (_LMA suffix).*/
42
43/* Flash region to be used for exception vectors.*/
44REGION_ALIAS("VECTORS_FLASH", flash0);
45REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
46
47/* Flash region to be used for constructors and destructors.*/
48REGION_ALIAS("XTORS_FLASH", flash0);
49REGION_ALIAS("XTORS_FLASH_LMA", flash0);
50
51/* Flash region to be used for code text.*/
52REGION_ALIAS("TEXT_FLASH", flash0);
53REGION_ALIAS("TEXT_FLASH_LMA", flash0);
54
55/* Flash region to be used for read only data.*/
56REGION_ALIAS("RODATA_FLASH", flash0);
57REGION_ALIAS("RODATA_FLASH_LMA", flash0);
58
59/* Flash region to be used for various.*/
60REGION_ALIAS("VARIOUS_FLASH", flash0);
61REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
62
63/* Flash region to be used for RAM(n) initialization data.*/
64REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
65
66/* RAM region to be used for Main stack. This stack accommodates the processing
67 of all exceptions and interrupts.*/
68REGION_ALIAS("MAIN_STACK_RAM", ram0);
69
70/* RAM region to be used for the process stack. This is the stack used by
71 the main() function.*/
72REGION_ALIAS("PROCESS_STACK_RAM", ram0);
73
74/* RAM region to be used for data segment.*/
75REGION_ALIAS("DATA_RAM", ram0);
76REGION_ALIAS("DATA_RAM_LMA", flash0);
77
78/* RAM region to be used for BSS segment.*/
79REGION_ALIAS("BSS_RAM", ram0);
80
81/* RAM region to be used for the default heap.*/
82REGION_ALIAS("HEAP_RAM", ram0);
83
84/* Generic rules inclusion.*/
85INCLUDE rules.ld
86
87/* TinyUF2 bootloader reset support */
88_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
89
diff --git a/platforms/chibios/GENERIC_STM32_F446XE/board/board.mk b/platforms/chibios/GENERIC_STM32_F446XE/board/board.mk
new file mode 100644
index 000000000..57897941c
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F446XE/board/board.mk
@@ -0,0 +1,9 @@
1# List of all the board related files.
2BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE/board.c
3
4# Required include directories
5BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE
6
7# Shared variables
8ALLCSRC += $(BOARDSRC)
9ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/GENERIC_STM32_F446XE/configs/board.h b/platforms/chibios/GENERIC_STM32_F446XE/configs/board.h
new file mode 100644
index 000000000..80dfcffa9
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F446XE/configs/board.h
@@ -0,0 +1,24 @@
1/* Copyright 2020 Nick Brassel (tzarc)
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 3 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <https://www.gnu.org/licenses/>.
15 */
16#pragma once
17
18#define STM32_HSECLK 16000000
19// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
20#define BOARD_OTG_NOVBUSSENS
21
22#include_next "board.h"
23
24#undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/GENERIC_STM32_F446XE/configs/config.h b/platforms/chibios/GENERIC_STM32_F446XE/configs/config.h
new file mode 100644
index 000000000..cc52a953e
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F446XE/configs/config.h
@@ -0,0 +1,23 @@
1/* Copyright 2021 Andrei Purdea
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Address for jumping to bootloader on STM32 chips. */
18/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
19 */
20#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
21#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
22# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
23#endif
diff --git a/platforms/chibios/GENERIC_STM32_F446XE/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_F446XE/configs/mcuconf.h
new file mode 100644
index 000000000..d2de75590
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F446XE/configs/mcuconf.h
@@ -0,0 +1,361 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#ifndef MCUCONF_H
18#define MCUCONF_H
19
20/*
21 * STM32F4xx drivers configuration.
22 * The following settings override the default settings present in
23 * the various device driver implementation headers.
24 * Note that the settings for each driver only have effect if the whole
25 * driver is enabled in halconf.h.
26 *
27 * IRQ priorities:
28 * 15...0 Lowest...Highest.
29 *
30 * DMA priorities:
31 * 0...3 Lowest...Highest.
32 */
33
34#define STM32F4xx_MCUCONF
35
36/*
37 * HAL driver system settings.
38 */
39#define STM32_NO_INIT FALSE
40#define STM32_HSI_ENABLED FALSE
41#define STM32_LSI_ENABLED TRUE
42#define STM32_HSE_ENABLED TRUE
43#define STM32_LSE_ENABLED FALSE
44#define STM32_CLOCK48_REQUIRED TRUE
45#define STM32_SW STM32_SW_PLL
46#define STM32_PLLSRC STM32_PLLSRC_HSE
47#define STM32_PLLM_VALUE 8
48#define STM32_PLLN_VALUE 180
49#define STM32_PLLP_VALUE 2
50#define STM32_PLLQ_VALUE 7
51#define STM32_PLLI2SN_VALUE 192
52#define STM32_PLLI2SM_VALUE 8
53#define STM32_PLLI2SR_VALUE 4
54#define STM32_PLLI2SP_VALUE 4
55#define STM32_PLLI2SQ_VALUE 4
56#define STM32_PLLSAIN_VALUE 192
57#define STM32_PLLSAIM_VALUE 8
58#define STM32_PLLSAIP_VALUE 8
59#define STM32_PLLSAIQ_VALUE 4
60#define STM32_HPRE STM32_HPRE_DIV1
61#define STM32_PPRE1 STM32_PPRE1_DIV4
62#define STM32_PPRE2 STM32_PPRE2_DIV2
63#define STM32_RTCSEL STM32_RTCSEL_LSI
64#define STM32_RTCPRE_VALUE 8
65#define STM32_MCO1SEL STM32_MCO1SEL_HSE
66#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
67#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
68#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
69#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
70#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
71#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
72#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT
73#define STM32_PVD_ENABLE FALSE
74#define STM32_PLS STM32_PLS_LEV0
75#define STM32_BKPRAM_ENABLE FALSE
76
77/*
78 * IRQ system settings.
79 */
80#define STM32_IRQ_EXTI0_PRIORITY 6
81#define STM32_IRQ_EXTI1_PRIORITY 6
82#define STM32_IRQ_EXTI2_PRIORITY 6
83#define STM32_IRQ_EXTI3_PRIORITY 6
84#define STM32_IRQ_EXTI4_PRIORITY 6
85#define STM32_IRQ_EXTI5_9_PRIORITY 6
86#define STM32_IRQ_EXTI10_15_PRIORITY 6
87#define STM32_IRQ_EXTI16_PRIORITY 6
88#define STM32_IRQ_EXTI17_PRIORITY 15
89#define STM32_IRQ_EXTI18_PRIORITY 6
90#define STM32_IRQ_EXTI19_PRIORITY 6
91#define STM32_IRQ_EXTI20_PRIORITY 6
92#define STM32_IRQ_EXTI21_PRIORITY 15
93#define STM32_IRQ_EXTI22_PRIORITY 15
94
95/*
96 * ADC driver system settings.
97 */
98#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
99#define STM32_ADC_USE_ADC1 FALSE
100#define STM32_ADC_USE_ADC2 FALSE
101#define STM32_ADC_USE_ADC3 FALSE
102#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
103#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
104#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
105#define STM32_ADC_ADC1_DMA_PRIORITY 2
106#define STM32_ADC_ADC2_DMA_PRIORITY 2
107#define STM32_ADC_ADC3_DMA_PRIORITY 2
108#define STM32_ADC_IRQ_PRIORITY 6
109#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
110#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
111#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
112
113/*
114 * CAN driver system settings.
115 */
116#define STM32_CAN_USE_CAN1 FALSE
117#define STM32_CAN_USE_CAN2 FALSE
118#define STM32_CAN_CAN1_IRQ_PRIORITY 11
119#define STM32_CAN_CAN2_IRQ_PRIORITY 11
120
121/*
122 * DAC driver system settings.
123 */
124#define STM32_DAC_DUAL_MODE FALSE
125#define STM32_DAC_USE_DAC1_CH1 FALSE
126#define STM32_DAC_USE_DAC1_CH2 FALSE
127#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
128#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
129#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
130#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
131#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
132#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
133
134/*
135 * GPT driver system settings.
136 */
137#define STM32_GPT_USE_TIM1 FALSE
138#define STM32_GPT_USE_TIM2 FALSE
139#define STM32_GPT_USE_TIM3 FALSE
140#define STM32_GPT_USE_TIM4 FALSE
141#define STM32_GPT_USE_TIM5 FALSE
142#define STM32_GPT_USE_TIM6 FALSE
143#define STM32_GPT_USE_TIM7 FALSE
144#define STM32_GPT_USE_TIM8 FALSE
145#define STM32_GPT_USE_TIM9 FALSE
146#define STM32_GPT_USE_TIM11 FALSE
147#define STM32_GPT_USE_TIM12 FALSE
148#define STM32_GPT_USE_TIM14 FALSE
149#define STM32_GPT_TIM1_IRQ_PRIORITY 7
150#define STM32_GPT_TIM2_IRQ_PRIORITY 7
151#define STM32_GPT_TIM3_IRQ_PRIORITY 7
152#define STM32_GPT_TIM4_IRQ_PRIORITY 7
153#define STM32_GPT_TIM5_IRQ_PRIORITY 7
154#define STM32_GPT_TIM6_IRQ_PRIORITY 7
155#define STM32_GPT_TIM7_IRQ_PRIORITY 7
156#define STM32_GPT_TIM8_IRQ_PRIORITY 7
157#define STM32_GPT_TIM9_IRQ_PRIORITY 7
158#define STM32_GPT_TIM11_IRQ_PRIORITY 7
159#define STM32_GPT_TIM12_IRQ_PRIORITY 7
160#define STM32_GPT_TIM14_IRQ_PRIORITY 7
161
162/*
163 * I2C driver system settings.
164 */
165#define STM32_I2C_USE_I2C1 FALSE
166#define STM32_I2C_USE_I2C2 FALSE
167#define STM32_I2C_USE_I2C3 FALSE
168#define STM32_I2C_BUSY_TIMEOUT 50
169#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
170#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
171#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
172#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
173#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
174#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
175#define STM32_I2C_I2C1_IRQ_PRIORITY 5
176#define STM32_I2C_I2C2_IRQ_PRIORITY 5
177#define STM32_I2C_I2C3_IRQ_PRIORITY 5
178#define STM32_I2C_I2C1_DMA_PRIORITY 3
179#define STM32_I2C_I2C2_DMA_PRIORITY 3
180#define STM32_I2C_I2C3_DMA_PRIORITY 3
181#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
182
183/*
184 * I2S driver system settings.
185 */
186#define STM32_I2S_USE_SPI2 FALSE
187#define STM32_I2S_USE_SPI3 FALSE
188#define STM32_I2S_SPI2_IRQ_PRIORITY 10
189#define STM32_I2S_SPI3_IRQ_PRIORITY 10
190#define STM32_I2S_SPI2_DMA_PRIORITY 1
191#define STM32_I2S_SPI3_DMA_PRIORITY 1
192#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
193#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
194#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
195#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
196#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
197
198/*
199 * ICU driver system settings.
200 */
201#define STM32_ICU_USE_TIM1 FALSE
202#define STM32_ICU_USE_TIM2 FALSE
203#define STM32_ICU_USE_TIM3 FALSE
204#define STM32_ICU_USE_TIM4 FALSE
205#define STM32_ICU_USE_TIM5 FALSE
206#define STM32_ICU_USE_TIM8 FALSE
207#define STM32_ICU_USE_TIM9 FALSE
208#define STM32_ICU_TIM1_IRQ_PRIORITY 7
209#define STM32_ICU_TIM2_IRQ_PRIORITY 7
210#define STM32_ICU_TIM3_IRQ_PRIORITY 7
211#define STM32_ICU_TIM4_IRQ_PRIORITY 7
212#define STM32_ICU_TIM5_IRQ_PRIORITY 7
213#define STM32_ICU_TIM8_IRQ_PRIORITY 7
214#define STM32_ICU_TIM9_IRQ_PRIORITY 7
215
216/*
217 * MAC driver system settings.
218 */
219#define STM32_MAC_TRANSMIT_BUFFERS 2
220#define STM32_MAC_RECEIVE_BUFFERS 4
221#define STM32_MAC_BUFFERS_SIZE 1522
222#define STM32_MAC_PHY_TIMEOUT 100
223#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
224#define STM32_MAC_ETH1_IRQ_PRIORITY 13
225#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
226
227/*
228 * PWM driver system settings.
229 */
230#define STM32_PWM_USE_ADVANCED FALSE
231#define STM32_PWM_USE_TIM1 FALSE
232#define STM32_PWM_USE_TIM2 FALSE
233#define STM32_PWM_USE_TIM3 FALSE
234#define STM32_PWM_USE_TIM4 FALSE
235#define STM32_PWM_USE_TIM5 FALSE
236#define STM32_PWM_USE_TIM8 FALSE
237#define STM32_PWM_USE_TIM9 FALSE
238#define STM32_PWM_TIM1_IRQ_PRIORITY 7
239#define STM32_PWM_TIM2_IRQ_PRIORITY 7
240#define STM32_PWM_TIM3_IRQ_PRIORITY 7
241#define STM32_PWM_TIM4_IRQ_PRIORITY 7
242#define STM32_PWM_TIM5_IRQ_PRIORITY 7
243#define STM32_PWM_TIM8_IRQ_PRIORITY 7
244#define STM32_PWM_TIM9_IRQ_PRIORITY 7
245
246/*
247 * SDC driver system settings.
248 */
249#define STM32_SDC_SDIO_DMA_PRIORITY 3
250#define STM32_SDC_SDIO_IRQ_PRIORITY 9
251#define STM32_SDC_WRITE_TIMEOUT_MS 1000
252#define STM32_SDC_READ_TIMEOUT_MS 1000
253#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
254#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
255#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
256
257/*
258 * SERIAL driver system settings.
259 */
260#define STM32_SERIAL_USE_USART1 FALSE
261#define STM32_SERIAL_USE_USART2 FALSE
262#define STM32_SERIAL_USE_USART3 FALSE
263#define STM32_SERIAL_USE_UART4 FALSE
264#define STM32_SERIAL_USE_UART5 FALSE
265#define STM32_SERIAL_USE_USART6 FALSE
266#define STM32_SERIAL_USE_UART7 FALSE
267#define STM32_SERIAL_USE_UART8 FALSE
268#define STM32_SERIAL_USART1_PRIORITY 12
269#define STM32_SERIAL_USART2_PRIORITY 12
270#define STM32_SERIAL_USART3_PRIORITY 12
271#define STM32_SERIAL_UART4_PRIORITY 12
272#define STM32_SERIAL_UART5_PRIORITY 12
273#define STM32_SERIAL_USART6_PRIORITY 12
274#define STM32_SERIAL_UART7_PRIORITY 12
275#define STM32_SERIAL_UART8_PRIORITY 12
276
277/*
278 * SPI driver system settings.
279 */
280#define STM32_SPI_USE_SPI1 FALSE
281#define STM32_SPI_USE_SPI2 FALSE
282#define STM32_SPI_USE_SPI3 FALSE
283#define STM32_SPI_USE_SPI4 FALSE
284#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
285#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
286#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
287#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
288#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
289#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
290#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
291#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
292#define STM32_SPI_SPI1_DMA_PRIORITY 1
293#define STM32_SPI_SPI2_DMA_PRIORITY 1
294#define STM32_SPI_SPI3_DMA_PRIORITY 1
295#define STM32_SPI_SPI4_DMA_PRIORITY 1
296#define STM32_SPI_SPI1_IRQ_PRIORITY 10
297#define STM32_SPI_SPI2_IRQ_PRIORITY 10
298#define STM32_SPI_SPI3_IRQ_PRIORITY 10
299#define STM32_SPI_SPI4_IRQ_PRIORITY 10
300#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
301
302/*
303 * ST driver system settings.
304 */
305#define STM32_ST_IRQ_PRIORITY 8
306#define STM32_ST_USE_TIMER 2
307
308/*
309 * UART driver system settings.
310 */
311#define STM32_UART_USE_USART1 FALSE
312#define STM32_UART_USE_USART2 FALSE
313#define STM32_UART_USE_USART3 FALSE
314#define STM32_UART_USE_UART4 FALSE
315#define STM32_UART_USE_UART5 FALSE
316#define STM32_UART_USE_USART6 FALSE
317#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
318#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
319#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
320#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
321#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
322#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
323#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
324#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
325#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
326#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
327#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
328#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
329#define STM32_UART_USART1_IRQ_PRIORITY 12
330#define STM32_UART_USART2_IRQ_PRIORITY 12
331#define STM32_UART_USART3_IRQ_PRIORITY 12
332#define STM32_UART_UART4_IRQ_PRIORITY 12
333#define STM32_UART_UART5_IRQ_PRIORITY 12
334#define STM32_UART_USART6_IRQ_PRIORITY 12
335#define STM32_UART_USART1_DMA_PRIORITY 0
336#define STM32_UART_USART2_DMA_PRIORITY 0
337#define STM32_UART_USART3_DMA_PRIORITY 0
338#define STM32_UART_UART4_DMA_PRIORITY 0
339#define STM32_UART_UART5_DMA_PRIORITY 0
340#define STM32_UART_USART6_DMA_PRIORITY 0
341#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
342
343/*
344 * USB driver system settings.
345 */
346#define STM32_USB_USE_OTG1 TRUE
347#define STM32_USB_USE_OTG2 FALSE
348#define STM32_USB_OTG1_IRQ_PRIORITY 14
349#define STM32_USB_OTG2_IRQ_PRIORITY 14
350#define STM32_USB_OTG1_RX_FIFO_SIZE 512
351#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
352#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
353#define STM32_USB_OTG_THREAD_STACK_SIZE 128
354#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
355
356/*
357 * WDG driver system settings.
358 */
359#define STM32_WDG_USE_IWDG FALSE
360
361#endif /* MCUCONF_H */
diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk
new file mode 100644
index 000000000..1250385eb
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk
@@ -0,0 +1,9 @@
1# List of all the board related files.
2BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
3
4# Required include directories
5BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
6
7# Shared variables
8ALLCSRC += $(BOARDSRC)
9ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h
new file mode 100644
index 000000000..51f9724f9
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h
@@ -0,0 +1,24 @@
1/* Copyright 2018-2021 Harrison Chan (@Xelus)
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 3 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <https://www.gnu.org/licenses/>.
15 */
16#pragma once
17
18#include_next "board.h"
19
20#undef STM32L432xx
21
22// Pretend that we're an L443xx as the ChibiOS definitions for L432/L433 mistakenly don't enable GPIOH, I2C2, or SPI2.
23// Until ChibiOS upstream is fixed, this should be kept at L443, as nothing in QMK currently utilises the crypto peripheral on the L443.
24#define STM32L443xx
diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h
new file mode 100644
index 000000000..c27c61b19
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h
@@ -0,0 +1,26 @@
1/* Copyright 2018-2021 Harrison Chan (@Xelus)
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Address for jumping to bootloader on STM32 chips. */
18/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
19 */
20#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
21
22#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
23
24#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
25# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
26#endif
diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h
new file mode 100644
index 000000000..948c740f6
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h
@@ -0,0 +1,292 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 http://www.apache.org/licenses/LICENSE-2.0
7 Unless required by applicable law or agreed to in writing, software
8 distributed under the License is distributed on an "AS IS" BASIS,
9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 See the License for the specific language governing permissions and
11 limitations under the License.
12*/
13
14/*
15 * STM32L4xx drivers configuration.
16 * The following settings override the default settings present in
17 * the various device driver implementation headers.
18 * Note that the settings for each driver only have effect if the whole
19 * driver is enabled in halconf.h.
20 *
21 * IRQ priorities:
22 * 15...0 Lowest...Highest.
23 *
24 * DMA priorities:
25 * 0...3 Lowest...Highest.
26 */
27
28#ifndef MCUCONF_H
29#define MCUCONF_H
30
31#define STM32L4xx_MCUCONF
32#define STM32L443_MCUCONF
33
34/*
35 * HAL driver system settings.
36 */
37#define STM32_NO_INIT FALSE
38#define STM32_VOS STM32_VOS_RANGE1
39#define STM32_PVD_ENABLE FALSE
40#define STM32_PLS STM32_PLS_LEV0
41#define STM32_HSI16_ENABLED TRUE
42#define STM32_HSI48_ENABLED TRUE
43#define STM32_LSI_ENABLED TRUE
44#define STM32_HSE_ENABLED FALSE
45#define STM32_LSE_ENABLED FALSE
46#define STM32_MSIPLL_ENABLED FALSE
47#define STM32_MSIRANGE STM32_MSIRANGE_4M
48#define STM32_MSISRANGE STM32_MSISRANGE_4M
49#define STM32_SW STM32_SW_PLL
50#define STM32_PLLSRC STM32_PLLSRC_HSI16
51#define STM32_PLLM_VALUE 1
52#define STM32_PLLN_VALUE 10
53#define STM32_PLLPDIV_VALUE 0
54#define STM32_PLLP_VALUE 7
55#define STM32_PLLQ_VALUE 2
56#define STM32_PLLR_VALUE 2
57#define STM32_HPRE STM32_HPRE_DIV1
58#define STM32_PPRE1 STM32_PPRE1_DIV1
59#define STM32_PPRE2 STM32_PPRE2_DIV1
60#define STM32_STOPWUCK STM32_STOPWUCK_MSI
61#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
62#define STM32_MCOPRE STM32_MCOPRE_DIV1
63#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
64#define STM32_PLLSAI1N_VALUE 24
65#define STM32_PLLSAI1PDIV_VALUE 0
66#define STM32_PLLSAI1P_VALUE 7
67#define STM32_PLLSAI1Q_VALUE 2
68#define STM32_PLLSAI1R_VALUE 2
69
70/*
71 * Peripherals clock sources.
72 */
73#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
74#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
75#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
76#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
77#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
78#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
79#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
80#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
81#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
82#define STM32_SAI1SEL STM32_SAI1SEL_OFF
83#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
84#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
85#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
86#define STM32_RTCSEL STM32_RTCSEL_LSI
87
88/*
89 * IRQ system settings.
90 */
91#define STM32_IRQ_EXTI0_PRIORITY 6
92#define STM32_IRQ_EXTI1_PRIORITY 6
93#define STM32_IRQ_EXTI2_PRIORITY 6
94#define STM32_IRQ_EXTI3_PRIORITY 6
95#define STM32_IRQ_EXTI4_PRIORITY 6
96#define STM32_IRQ_EXTI5_9_PRIORITY 6
97#define STM32_IRQ_EXTI10_15_PRIORITY 6
98#define STM32_IRQ_EXTI1635_38_PRIORITY 6
99#define STM32_IRQ_EXTI18_PRIORITY 6
100#define STM32_IRQ_EXTI19_PRIORITY 6
101#define STM32_IRQ_EXTI20_PRIORITY 6
102#define STM32_IRQ_EXTI21_22_PRIORITY 15
103
104#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
105#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
106#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
107#define STM32_IRQ_TIM1_CC_PRIORITY 7
108#define STM32_IRQ_TIM2_PRIORITY 7
109#define STM32_IRQ_TIM6_PRIORITY 7
110#define STM32_IRQ_TIM7_PRIORITY 7
111
112#define STM32_IRQ_USART1_PRIORITY 12
113#define STM32_IRQ_USART2_PRIORITY 12
114#define STM32_IRQ_USART3_PRIORITY 12
115#define STM32_IRQ_LPUART1_PRIORITY 12
116
117/*
118 * ADC driver system settings.
119 */
120#define STM32_ADC_COMPACT_SAMPLES FALSE
121#define STM32_ADC_USE_ADC1 FALSE
122#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
123#define STM32_ADC_ADC1_DMA_PRIORITY 2
124#define STM32_ADC_ADC12_IRQ_PRIORITY 5
125#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
126#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
127#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
128
129/*
130 * CAN driver system settings.
131 */
132#define STM32_CAN_USE_CAN1 FALSE
133#define STM32_CAN_CAN1_IRQ_PRIORITY 11
134
135/*
136 * DAC driver system settings.
137 */
138#define STM32_DAC_DUAL_MODE FALSE
139#define STM32_DAC_USE_DAC1_CH1 FALSE
140#define STM32_DAC_USE_DAC1_CH2 FALSE
141#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
142#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
143#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
144#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
145#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
146#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
147
148/*
149 * GPT driver system settings.
150 */
151#define STM32_GPT_USE_TIM1 FALSE
152#define STM32_GPT_USE_TIM2 FALSE
153#define STM32_GPT_USE_TIM6 FALSE
154#define STM32_GPT_USE_TIM7 FALSE
155#define STM32_GPT_USE_TIM15 FALSE
156#define STM32_GPT_USE_TIM16 FALSE
157
158/*
159 * I2C driver system settings.
160 */
161#define STM32_I2C_USE_I2C1 FALSE
162#define STM32_I2C_USE_I2C2 FALSE
163#define STM32_I2C_USE_I2C3 FALSE
164#define STM32_I2C_BUSY_TIMEOUT 50
165#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
166#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
167#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
168#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
169#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
170#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
171#define STM32_I2C_I2C1_IRQ_PRIORITY 5
172#define STM32_I2C_I2C2_IRQ_PRIORITY 5
173#define STM32_I2C_I2C3_IRQ_PRIORITY 5
174#define STM32_I2C_I2C1_DMA_PRIORITY 3
175#define STM32_I2C_I2C2_DMA_PRIORITY 3
176#define STM32_I2C_I2C3_DMA_PRIORITY 3
177#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
178
179/*
180 * ICU driver system settings.
181 */
182#define STM32_ICU_USE_TIM1 FALSE
183#define STM32_ICU_USE_TIM2 FALSE
184#define STM32_ICU_USE_TIM15 FALSE
185#define STM32_ICU_USE_TIM16 FALSE
186
187/*
188 * PWM driver system settings.
189 */
190#define STM32_PWM_USE_ADVANCED FALSE
191#define STM32_PWM_USE_TIM1 FALSE
192#define STM32_PWM_USE_TIM2 FALSE
193#define STM32_PWM_USE_TIM15 FALSE
194#define STM32_PWM_USE_TIM16 FALSE
195
196/*
197 * RTC driver system settings.
198 */
199#define STM32_RTC_PRESA_VALUE 32
200#define STM32_RTC_PRESS_VALUE 1024
201#define STM32_RTC_CR_INIT 0
202#define STM32_RTC_TAMPCR_INIT 0
203
204/*
205 * SDMMC drive system settings.
206 */
207#define STM32_SDC_USE_SDMMC1 FALSE
208#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
209#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
210#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
211#define STM32_SDC_SDMMC_CLOCK_DELAY 10
212#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
213#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
214#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
215
216/*
217 * SERIAL driver system settings.
218 */
219#define STM32_SERIAL_USE_USART1 FALSE
220#define STM32_SERIAL_USE_USART2 FALSE
221#define STM32_SERIAL_USE_USART3 FALSE
222#define STM32_SERIAL_USE_LPUART1 FALSE
223#define STM32_SERIAL_USART1_PRIORITY 12
224#define STM32_SERIAL_USART2_PRIORITY 12
225#define STM32_SERIAL_USART3_PRIORITY 12
226#define STM32_SERIAL_LPUART1_PRIORITY 12
227
228/*
229 * SPI driver system settings.
230 */
231#define STM32_SPI_USE_SPI1 FALSE
232#define STM32_SPI_USE_SPI2 FALSE
233#define STM32_SPI_USE_SPI3 FALSE
234#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
235#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
236#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
237#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
238#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
239#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
240#define STM32_SPI_SPI1_DMA_PRIORITY 1
241#define STM32_SPI_SPI2_DMA_PRIORITY 1
242#define STM32_SPI_SPI3_DMA_PRIORITY 1
243#define STM32_SPI_SPI1_IRQ_PRIORITY 10
244#define STM32_SPI_SPI2_IRQ_PRIORITY 10
245#define STM32_SPI_SPI3_IRQ_PRIORITY 10
246#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
247
248/*
249 * ST driver system settings.
250 */
251#define STM32_ST_IRQ_PRIORITY 8
252#define STM32_ST_USE_TIMER 2
253
254/*
255 * TRNG driver system settings.
256 */
257#define STM32_TRNG_USE_RNG1 FALSE
258
259/*
260 * UART driver system settings.
261 */
262#define STM32_UART_USE_USART1 FALSE
263#define STM32_UART_USE_USART2 FALSE
264#define STM32_UART_USE_USART3 FALSE
265#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
266#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
267#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
268#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
269#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
270#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
271#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
272
273/*
274 * USB driver system settings.
275 */
276#define STM32_USB_USE_USB1 TRUE
277#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
278#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
279#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
280
281/*
282 * WDG driver system settings.
283 */
284#define STM32_WDG_USE_IWDG FALSE
285
286/*
287 * WSPI driver system settings.
288 */
289#define STM32_WSPI_USE_QUADSPI1 FALSE
290#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
291
292#endif /* MCUCONF_H */
diff --git a/platforms/chibios/QMK_PROTON_C/convert_to_proton_c.mk b/platforms/chibios/QMK_PROTON_C/convert_to_proton_c.mk
index 3fa73a96e..d0a337bad 100644
--- a/platforms/chibios/QMK_PROTON_C/convert_to_proton_c.mk
+++ b/platforms/chibios/QMK_PROTON_C/convert_to_proton_c.mk
@@ -5,8 +5,5 @@ BOARD := QMK_PROTON_C
5OPT_DEFS += -DCONVERT_TO_PROTON_C 5OPT_DEFS += -DCONVERT_TO_PROTON_C
6 6
7# These are defaults based on what has been implemented for ARM boards 7# These are defaults based on what has been implemented for ARM boards
8AUDIO_ENABLE = yes 8AUDIO_ENABLE ?= yes
9WS2812_DRIVER = bitbang 9WS2812_DRIVER ?= bitbang
10
11# Force task driven PWM until ARM can provide automatic configuration
12BACKLIGHT_DRIVER = software \ No newline at end of file
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-05 05:28:15 +0000