40 files changed, 3047 insertions, 93 deletions
diff --git a/platforms/arm_atsam/flash.mk b/platforms/arm_atsam/flash.mk
index f31d4b4d9..8152610ce 100644
--- a/platforms/arm_atsam/flash.mk
+++ b/platforms/arm_atsam/flash.mk
@@ -3,9 +3,20 @@
 # Architecture or project specific options
 #
+MDLOADER_CLI ?= mdloader
+define EXEC_MDLOADER
+        $(MDLOADER_CLI) --first --download $(BUILD_DIR)/$(TARGET).bin --restart
+endef
+mdloader: bin
+        $(call EXEC_MDLOADER)
 flash: bin
 ifneq ($(strip $(PROGRAM_CMD)),)
        $(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
+else ifeq ($(strip $(ARM_ATSAM)),SAMD51J18A)
+        $(UNSYNC_OUTPUT_CMD) && $(call EXEC_MDLOADER)
 else
        $(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_ARCH)"
 endif
diff --git a/platforms/avr/drivers/analog.c b/platforms/avr/drivers/analog.c
index 8d299ffdb..628835cce 100644
--- a/platforms/avr/drivers/analog.c
+++ b/platforms/avr/drivers/analog.c
@@ -23,29 +23,6 @@ static uint8_t aref = ADC_REF_POWER;
 void analogReference(uint8_t mode) { aref = mode & (_BV(REFS1) | _BV(REFS0)); }
-// Arduino compatible pin input
-int16_t analogRead(uint8_t pin) {
-#if defined(__AVR_ATmega32U4__)
-    // clang-format off
-    static const uint8_t PROGMEM pin_to_mux[] = {
-        //A0    A1    A2    A3    A4    A5
-        //F7    F6    F5    F4    F1    F0
-        0x07, 0x06, 0x05, 0x04, 0x01, 0x00,
-        //A6    A7    A8    A9   A10   A11
-        //D4    D7    B4    B5    B6    D6
-        0x20, 0x22, 0x23, 0x24, 0x25, 0x21
-    };
-    // clang-format on
-    if (pin >= 12) return 0;
-    return adc_read(pgm_read_byte(pin_to_mux + pin));
-#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328__)
-    if (pin >= 8) return 0;
-    return adc_read(pin);
-#else
-    return 0;
-#endif
-}
 int16_t analogReadPin(pin_t pin) { return adc_read(pinToMux(pin)); }
 uint8_t pinToMux(pin_t pin) {
diff --git a/platforms/avr/drivers/analog.h b/platforms/avr/drivers/analog.h
index 058882450..b3c05e197 100644
--- a/platforms/avr/drivers/analog.h
+++ b/platforms/avr/drivers/analog.h
@@ -23,7 +23,6 @@
 extern "C" {
 #endif
 void    analogReference(uint8_t mode);
-int16_t analogRead(uint8_t pin);
 int16_t analogReadPin(pin_t pin);
 uint8_t pinToMux(pin_t pin);
diff --git a/platforms/avr/drivers/audio_pwm.h b/platforms/avr/drivers/audio_pwm.h
new file mode 100644
index 000000000..d6eb3571d
--- /dev/null
+++ b/platforms/avr/drivers/audio_pwm.h
@@ -0,0 +1,17 @@
+/* Copyright 2020 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
diff --git a/platforms/avr/drivers/audio_pwm_hardware.c b/platforms/avr/drivers/audio_pwm_hardware.c
new file mode 100644
index 000000000..df03a4558
--- /dev/null
+++ b/platforms/avr/drivers/audio_pwm_hardware.c
@@ -0,0 +1,332 @@
+/* Copyright 2016 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#if defined(__AVR__)
+#    include <avr/pgmspace.h>
+#    include <avr/interrupt.h>
+#    include <avr/io.h>
+#endif
+#include "audio.h"
+extern bool    playing_note;
+extern bool    playing_melody;
+extern uint8_t note_timbre;
+#define CPU_PRESCALER 8
+/*
+  Audio Driver: PWM
+  drive up to two speakers through the AVR PWM hardware-peripheral, using timer1 and/or timer3 on Atmega32U4.
+  the primary channel_1 can be connected to either pin PC4 PC5 or PC6 (the later being used by most AVR based keyboards) with a PMW signal generated by timer3
+  and an optional secondary channel_2 on either pin PB5, PB6 or PB7, with a PWM signal from timer1
+  alternatively, the PWM pins on PORTB can be used as only/primary speaker
+*/
+#if defined(AUDIO_PIN) && (AUDIO_PIN != C4) && (AUDIO_PIN != C5) && (AUDIO_PIN != C6) && (AUDIO_PIN != B5) && (AUDIO_PIN != B6) && (AUDIO_PIN != B7) && (AUDIO_PIN != D5)
+#    error "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under the AVR settings for available options."
+#endif
+#if (AUDIO_PIN == C4) || (AUDIO_PIN == C5) || (AUDIO_PIN == C6)
+#    define AUDIO1_PIN_SET
+#    define AUDIO1_TIMSKx TIMSK3
+#    define AUDIO1_TCCRxA TCCR3A
+#    define AUDIO1_TCCRxB TCCR3B
+#    define AUDIO1_ICRx ICR3
+#    define AUDIO1_WGMx0 WGM30
+#    define AUDIO1_WGMx1 WGM31
+#    define AUDIO1_WGMx2 WGM32
+#    define AUDIO1_WGMx3 WGM33
+#    define AUDIO1_CSx0 CS30
+#    define AUDIO1_CSx1 CS31
+#    define AUDIO1_CSx2 CS32
+#    if (AUDIO_PIN == C6)
+#        define AUDIO1_COMxy0 COM3A0
+#        define AUDIO1_COMxy1 COM3A1
+#        define AUDIO1_OCIExy OCIE3A
+#        define AUDIO1_OCRxy OCR3A
+#        define AUDIO1_PIN C6
+#        define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPA_vect
+#    elif (AUDIO_PIN == C5)
+#        define AUDIO1_COMxy0 COM3B0
+#        define AUDIO1_COMxy1 COM3B1
+#        define AUDIO1_OCIExy OCIE3B
+#        define AUDIO1_OCRxy OCR3B
+#        define AUDIO1_PIN C5
+#        define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPB_vect
+#    elif (AUDIO_PIN == C4)
+#        define AUDIO1_COMxy0 COM3C0
+#        define AUDIO1_COMxy1 COM3C1
+#        define AUDIO1_OCIExy OCIE3C
+#        define AUDIO1_OCRxy OCR3C
+#        define AUDIO1_PIN C4
+#        define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPC_vect
+#    endif
+#endif
+#if defined(AUDIO_PIN) && defined(AUDIO_PIN_ALT) && (AUDIO_PIN == AUDIO_PIN_ALT)
+#    error "Audio feature: AUDIO_PIN and AUDIO_PIN_ALT on the same pin makes no sense."
+#endif
+#if ((AUDIO_PIN == B5) && ((AUDIO_PIN_ALT == B6) || (AUDIO_PIN_ALT == B7))) || ((AUDIO_PIN == B6) && ((AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B7))) || ((AUDIO_PIN == B7) && ((AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B6)))
+#    error "Audio feature: PORTB as AUDIO_PIN and AUDIO_PIN_ALT at the same time is not supported."
+#endif
+#if defined(AUDIO_PIN_ALT) && (AUDIO_PIN_ALT != B5) && (AUDIO_PIN_ALT != B6) && (AUDIO_PIN_ALT != B7)
+#    error "Audio feature: the pin selected as AUDIO_PIN_ALT is not supported."
+#endif
+#if (AUDIO_PIN == B5) || (AUDIO_PIN == B6) || (AUDIO_PIN == B7) || (AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B6) || (AUDIO_PIN_ALT == B7) || (AUDIO_PIN == D5)
+#    define AUDIO2_PIN_SET
+#    define AUDIO2_TIMSKx TIMSK1
+#    define AUDIO2_TCCRxA TCCR1A
+#    define AUDIO2_TCCRxB TCCR1B
+#    define AUDIO2_ICRx ICR1
+#    define AUDIO2_WGMx0 WGM10
+#    define AUDIO2_WGMx1 WGM11
+#    define AUDIO2_WGMx2 WGM12
+#    define AUDIO2_WGMx3 WGM13
+#    define AUDIO2_CSx0 CS10
+#    define AUDIO2_CSx1 CS11
+#    define AUDIO2_CSx2 CS12
+#    if (AUDIO_PIN == B5) || (AUDIO_PIN_ALT == B5)
+#        define AUDIO2_COMxy0 COM1A0
+#        define AUDIO2_COMxy1 COM1A1
+#        define AUDIO2_OCIExy OCIE1A
+#        define AUDIO2_OCRxy OCR1A
+#        define AUDIO2_PIN B5
+#        define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPA_vect
+#    elif (AUDIO_PIN == B6) || (AUDIO_PIN_ALT == B6)
+#        define AUDIO2_COMxy0 COM1B0
+#        define AUDIO2_COMxy1 COM1B1
+#        define AUDIO2_OCIExy OCIE1B
+#        define AUDIO2_OCRxy OCR1B
+#        define AUDIO2_PIN B6
+#        define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPB_vect
+#    elif (AUDIO_PIN == B7) || (AUDIO_PIN_ALT == B7)
+#        define AUDIO2_COMxy0 COM1C0
+#        define AUDIO2_COMxy1 COM1C1
+#        define AUDIO2_OCIExy OCIE1C
+#        define AUDIO2_OCRxy OCR1C
+#        define AUDIO2_PIN B7
+#        define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPC_vect
+#    elif (AUDIO_PIN == D5) && defined(__AVR_ATmega32A__)
+#        pragma message "Audio support for ATmega32A is experimental and can cause crashes."
+#        undef AUDIO2_TIMSKx
+#        define AUDIO2_TIMSKx TIMSK
+#        define AUDIO2_COMxy0 COM1A0
+#        define AUDIO2_COMxy1 COM1A1
+#        define AUDIO2_OCIExy OCIE1A
+#        define AUDIO2_OCRxy OCR1A
+#        define AUDIO2_PIN D5
+#        define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPA_vect
+#    endif
+#endif
+// C6 seems to be the assumed default by many existing keyboard - but sill warn the user
+#if !defined(AUDIO1_PIN_SET) && !defined(AUDIO2_PIN_SET)
+#    pragma message "Audio feature enabled, but no suitable pin selected - see docs/feature_audio under the AVR settings for available options. Don't expect to hear anything... :-)"
+// TODO: make this an error - go through the breaking-change-process and change all keyboards to the new define
+#endif
+// -----------------------------------------------------------------------------
+#ifdef AUDIO1_PIN_SET
+static float channel_1_frequency = 0.0f;
+void         channel_1_set_frequency(float freq) {
+    if (freq == 0.0f)  // a pause/rest is a valid "note" with freq=0
+    {
+        // disable the output, but keep the pwm-ISR going (with the previous
+        // frequency) so the audio-state keeps getting updated
+        // Note: setting the duty-cycle 0 is not possible on non-inverting PWM mode - see the AVR data-sheet
+        AUDIO1_TCCRxA &= ~(_BV(AUDIO1_COMxy1) | _BV(AUDIO1_COMxy0));
+        return;
+    } else {
+        AUDIO1_TCCRxA |= _BV(AUDIO1_COMxy1);  // enable output, PWM mode
+    }
+    channel_1_frequency = freq;
+    // set pwm period
+    AUDIO1_ICRx = (uint16_t)(((float)F_CPU) / (freq * CPU_PRESCALER));
+    // and duty cycle
+    AUDIO1_OCRxy = (uint16_t)((((float)F_CPU) / (freq * CPU_PRESCALER)) * note_timbre / 100);
+}
+void channel_1_start(void) {
+    // enable timer-counter ISR
+    AUDIO1_TIMSKx |= _BV(AUDIO1_OCIExy);
+    // enable timer-counter output
+    AUDIO1_TCCRxA |= _BV(AUDIO1_COMxy1);
+}
+void channel_1_stop(void) {
+    // disable timer-counter ISR
+    AUDIO1_TIMSKx &= ~_BV(AUDIO1_OCIExy);
+    // disable timer-counter output
+    AUDIO1_TCCRxA &= ~(_BV(AUDIO1_COMxy1) | _BV(AUDIO1_COMxy0));
+}
+#endif
+#ifdef AUDIO2_PIN_SET
+static float channel_2_frequency = 0.0f;
+void         channel_2_set_frequency(float freq) {
+    if (freq == 0.0f) {
+        AUDIO2_TCCRxA &= ~(_BV(AUDIO2_COMxy1) | _BV(AUDIO2_COMxy0));
+        return;
+    } else {
+        AUDIO2_TCCRxA |= _BV(AUDIO2_COMxy1);
+    }
+    channel_2_frequency = freq;
+    AUDIO2_ICRx  = (uint16_t)(((float)F_CPU) / (freq * CPU_PRESCALER));
+    AUDIO2_OCRxy = (uint16_t)((((float)F_CPU) / (freq * CPU_PRESCALER)) * note_timbre / 100);
+}
+float channel_2_get_frequency(void) { return channel_2_frequency; }
+void channel_2_start(void) {
+    AUDIO2_TIMSKx |= _BV(AUDIO2_OCIExy);
+    AUDIO2_TCCRxA |= _BV(AUDIO2_COMxy1);
+}
+void channel_2_stop(void) {
+    AUDIO2_TIMSKx &= ~_BV(AUDIO2_OCIExy);
+    AUDIO2_TCCRxA &= ~(_BV(AUDIO2_COMxy1) | _BV(AUDIO2_COMxy0));
+}
+#endif
+void audio_driver_initialize() {
+#ifdef AUDIO1_PIN_SET
+    channel_1_stop();
+    setPinOutput(AUDIO1_PIN);
+#endif
+#ifdef AUDIO2_PIN_SET
+    channel_2_stop();
+    setPinOutput(AUDIO2_PIN);
+#endif
+    // TCCR3A / TCCR3B: Timer/Counter #3 Control Registers TCCR3A/TCCR3B, TCCR1A/TCCR1B
+    // Compare Output Mode (COM3An and COM1An) = 0b00 = Normal port operation
+    //   OC3A -- PC6
+    //   OC3B -- PC5
+    //   OC3C -- PC4
+    //   OC1A -- PB5
+    //   OC1B -- PB6
+    //   OC1C -- PB7
+    // Waveform Generation Mode (WGM3n) = 0b1110 = Fast PWM Mode 14. Period = ICR3, Duty Cycle OCR3A)
+    //   OCR3A - PC6
+    //   OCR3B - PC5
+    //   OCR3C - PC4
+    //   OCR1A - PB5
+    //   OCR1B - PB6
+    //   OCR1C - PB7
+    // Clock Select (CS3n) = 0b010 = Clock / 8
+#ifdef AUDIO1_PIN_SET
+    // initialize timer-counter
+    AUDIO1_TCCRxA = (0 << AUDIO1_COMxy1) | (0 << AUDIO1_COMxy0) | (1 << AUDIO1_WGMx1) | (0 << AUDIO1_WGMx0);
+    AUDIO1_TCCRxB = (1 << AUDIO1_WGMx3) | (1 << AUDIO1_WGMx2) | (0 << AUDIO1_CSx2) | (1 << AUDIO1_CSx1) | (0 << AUDIO1_CSx0);
+#endif
+#ifdef AUDIO2_PIN_SET
+    AUDIO2_TCCRxA = (0 << AUDIO2_COMxy1) | (0 << AUDIO2_COMxy0) | (1 << AUDIO2_WGMx1) | (0 << AUDIO2_WGMx0);
+    AUDIO2_TCCRxB = (1 << AUDIO2_WGMx3) | (1 << AUDIO2_WGMx2) | (0 << AUDIO2_CSx2) | (1 << AUDIO2_CSx1) | (0 << AUDIO2_CSx0);
+#endif
+}
+void audio_driver_stop() {
+#ifdef AUDIO1_PIN_SET
+    channel_1_stop();
+#endif
+#ifdef AUDIO2_PIN_SET
+    channel_2_stop();
+#endif
+}
+void audio_driver_start(void) {
+#ifdef AUDIO1_PIN_SET
+    channel_1_start();
+    if (playing_note) {
+        channel_1_set_frequency(audio_get_processed_frequency(0));
+    }
+#endif
+#if !defined(AUDIO1_PIN_SET) && defined(AUDIO2_PIN_SET)
+    channel_2_start();
+    if (playing_note) {
+        channel_2_set_frequency(audio_get_processed_frequency(0));
+    }
+#endif
+}
+static volatile uint32_t isr_counter = 0;
+#ifdef AUDIO1_PIN_SET
+ISR(AUDIO1_TIMERx_COMPy_vect) {
+    isr_counter++;
+    if (isr_counter < channel_1_frequency / (CPU_PRESCALER * 8)) return;
+    isr_counter        = 0;
+    bool state_changed = audio_update_state();
+    if (!playing_note && !playing_melody) {
+        channel_1_stop();
+#    ifdef AUDIO2_PIN_SET
+        channel_2_stop();
+#    endif
+        return;
+    }
+    if (state_changed) {
+        channel_1_set_frequency(audio_get_processed_frequency(0));
+#    ifdef AUDIO2_PIN_SET
+        if (audio_get_number_of_active_tones() > 1) {
+            channel_2_set_frequency(audio_get_processed_frequency(1));
+        } else {
+            channel_2_stop();
+        }
+#    endif
+    }
+}
+#endif
+#if !defined(AUDIO1_PIN_SET) && defined(AUDIO2_PIN_SET)
+ISR(AUDIO2_TIMERx_COMPy_vect) {
+    isr_counter++;
+    if (isr_counter < channel_2_frequency / (CPU_PRESCALER * 8)) return;
+    isr_counter        = 0;
+    bool state_changed = audio_update_state();
+    if (!playing_note && !playing_melody) {
+        channel_2_stop();
+        return;
+    }
+    if (state_changed) {
+        channel_2_set_frequency(audio_get_processed_frequency(0));
+    }
+}
+#endif
diff --git a/platforms/avr/drivers/i2c_master.c b/platforms/avr/drivers/i2c_master.c
index 2773e0077..111b55d6b 100644
--- a/platforms/avr/drivers/i2c_master.c
+++ b/platforms/avr/drivers/i2c_master.c
@@ -202,6 +202,25 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
    return status;
 }
+i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
+    i2c_status_t status = i2c_start(devaddr | 0x00, timeout);
+    if (status >= 0) {
+        status = i2c_write(regaddr >> 8, timeout);
+        if (status >= 0) {
+            status = i2c_write(regaddr & 0xFF, timeout);
+            for (uint16_t i = 0; i < length && status >= 0; i++) {
+                status = i2c_write(data[i], timeout);
+            }
+        }
+    }
+    i2c_stop();
+    return status;
+}
 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
    i2c_status_t status = i2c_start(devaddr, timeout);
    if (status < 0) {
@@ -235,6 +254,43 @@ error:
    return (status < 0) ? status : I2C_STATUS_SUCCESS;
 }
+i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
+    i2c_status_t status = i2c_start(devaddr, timeout);
+    if (status < 0) {
+        goto error;
+    }
+    status = i2c_write(regaddr >> 8, timeout);
+    if (status < 0) {
+        goto error;
+    }
+    status = i2c_write(regaddr & 0xFF, timeout);
+    if (status < 0) {
+        goto error;
+    }
+    status = i2c_start(devaddr | 0x01, timeout);
+    for (uint16_t i = 0; i < (length - 1) && status >= 0; i++) {
+        status = i2c_read_ack(timeout);
+        if (status >= 0) {
+            data[i] = status;
+        }
+    }
+    if (status >= 0) {
+        status = i2c_read_nack(timeout);
+        if (status >= 0) {
+            data[(length - 1)] = status;
+        }
+    }
+error:
+    i2c_stop();
+    return (status < 0) ? status : I2C_STATUS_SUCCESS;
+}
 void i2c_stop(void) {
    // transmit STOP condition
    TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);
diff --git a/platforms/avr/drivers/i2c_master.h b/platforms/avr/drivers/i2c_master.h
index e5af73364..2d95846db 100644
--- a/platforms/avr/drivers/i2c_master.h
+++ b/platforms/avr/drivers/i2c_master.h
@@ -39,5 +39,7 @@ int16_t      i2c_read_nack(uint16_t timeout);
 i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
 void         i2c_stop(void);
diff --git a/platforms/avr/drivers/ps2/ps2_io.c b/platforms/avr/drivers/ps2/ps2_io.c
new file mode 100644
index 000000000..7c826fbf1
--- /dev/null
+++ b/platforms/avr/drivers/ps2/ps2_io.c
@@ -0,0 +1,51 @@
+#include <stdbool.h>
+#include "ps2_io.h"
+#include "gpio.h"
+#include "wait.h"
+/* Check port settings for clock and data line */
+#if !(defined(PS2_CLOCK_PIN))
+#    error "PS/2 clock setting is required in config.h"
+#endif
+#if !(defined(PS2_DATA_PIN))
+#    error "PS/2 data setting is required in config.h"
+#endif
+/*
+ * Clock
+ */
+void clock_init(void) {}
+void clock_lo(void) {
+    // Transition from input with pull-up to output low via Hi-Z instead of output high
+    writePinLow(PS2_CLOCK_PIN);
+    setPinOutput(PS2_CLOCK_PIN);
+}
+void clock_hi(void) { setPinInputHigh(PS2_CLOCK_PIN); }
+bool clock_in(void) {
+    setPinInputHigh(PS2_CLOCK_PIN);
+    wait_us(1);
+    return readPin(PS2_CLOCK_PIN);
+}
+/*
+ * Data
+ */
+void data_init(void) {}
+void data_lo(void) {
+    // Transition from input with pull-up to output low via Hi-Z instead of output high
+    writePinLow(PS2_DATA_PIN);
+    setPinOutput(PS2_DATA_PIN);
+}
+void data_hi(void) { setPinInputHigh(PS2_DATA_PIN); }
+bool data_in(void) {
+    setPinInputHigh(PS2_DATA_PIN);
+    wait_us(1);
+    return readPin(PS2_DATA_PIN);
+}
diff --git a/platforms/avr/drivers/ps2/ps2_usart.c b/platforms/avr/drivers/ps2/ps2_usart.c
new file mode 100644
index 000000000..151cfcd68
--- /dev/null
+++ b/platforms/avr/drivers/ps2/ps2_usart.c
@@ -0,0 +1,227 @@
+/*
+Copyright 2010,2011,2012,2013 Jun WAKO <wakojun@gmail.com>
+This software is licensed with a Modified BSD License.
+All of this is supposed to be Free Software, Open Source, DFSG-free,
+GPL-compatible, and OK to use in both free and proprietary applications.
+Additions and corrections to this file are welcome.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+* Neither the name of the copyright holders nor the names of
+  contributors may be used to endorse or promote products derived
+  from this software without specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * PS/2 protocol USART version
+ */
+#include <stdbool.h>
+#include <avr/interrupt.h>
+#include <util/delay.h>
+#include "gpio.h"
+#include "ps2.h"
+#include "ps2_io.h"
+#include "print.h"
+#ifndef PS2_CLOCK_DDR
+#    define PS2_CLOCK_DDR PORTx_ADDRESS(PS2_CLOCK_PIN)
+#endif
+#ifndef PS2_CLOCK_BIT
+#    define PS2_CLOCK_BIT (PS2_CLOCK_PIN & 0xF)
+#endif
+#ifndef PS2_DATA_DDR
+#    define PS2_DATA_DDR PORTx_ADDRESS(PS2_DATA_PIN)
+#endif
+#ifndef PS2_DATA_BIT
+#    define PS2_DATA_BIT (PS2_DATA_PIN & 0xF)
+#endif
+#define WAIT(stat, us, err)     \
+    do {                        \
+        if (!wait_##stat(us)) { \
+            ps2_error = err;    \
+            goto ERROR;         \
+        }                       \
+    } while (0)
+uint8_t ps2_error = PS2_ERR_NONE;
+static inline uint8_t pbuf_dequeue(void);
+static inline void    pbuf_enqueue(uint8_t data);
+static inline bool    pbuf_has_data(void);
+static inline void    pbuf_clear(void);
+void ps2_host_init(void) {
+    idle();  // without this many USART errors occur when cable is disconnected
+    PS2_USART_INIT();
+    PS2_USART_RX_INT_ON();
+    // POR(150-2000ms) plus BAT(300-500ms) may take 2.5sec([3]p.20)
+    //_delay_ms(2500);
+}
+uint8_t ps2_host_send(uint8_t data) {
+    bool parity = true;
+    ps2_error   = PS2_ERR_NONE;
+    PS2_USART_OFF();
+    /* terminate a transmission if we have */
+    inhibit();
+    _delay_us(100);  // [4]p.13
+    /* 'Request to Send' and Start bit */
+    data_lo();
+    clock_hi();
+    WAIT(clock_lo, 10000, 10);  // 10ms [5]p.50
+    /* Data bit[2-9] */
+    for (uint8_t i = 0; i < 8; i++) {
+        _delay_us(15);
+        if (data & (1 << i)) {
+            parity = !parity;
+            data_hi();
+        } else {
+            data_lo();
+        }
+        WAIT(clock_hi, 50, 2);
+        WAIT(clock_lo, 50, 3);
+    }
+    /* Parity bit */
+    _delay_us(15);
+    if (parity) {
+        data_hi();
+    } else {
+        data_lo();
+    }
+    WAIT(clock_hi, 50, 4);
+    WAIT(clock_lo, 50, 5);
+    /* Stop bit */
+    _delay_us(15);
+    data_hi();
+    /* Ack */
+    WAIT(data_lo, 50, 6);
+    WAIT(clock_lo, 50, 7);
+    /* wait for idle state */
+    WAIT(clock_hi, 50, 8);
+    WAIT(data_hi, 50, 9);
+    idle();
+    PS2_USART_INIT();
+    PS2_USART_RX_INT_ON();
+    return ps2_host_recv_response();
+ERROR:
+    idle();
+    PS2_USART_INIT();
+    PS2_USART_RX_INT_ON();
+    return 0;
+}
+uint8_t ps2_host_recv_response(void) {
+    // Command may take 25ms/20ms at most([5]p.46, [3]p.21)
+    uint8_t retry = 25;
+    while (retry-- && !pbuf_has_data()) {
+        _delay_ms(1);
+    }
+    return pbuf_dequeue();
+}
+uint8_t ps2_host_recv(void) {
+    if (pbuf_has_data()) {
+        ps2_error = PS2_ERR_NONE;
+        return pbuf_dequeue();
+    } else {
+        ps2_error = PS2_ERR_NODATA;
+        return 0;
+    }
+}
+ISR(PS2_USART_RX_VECT) {
+    // TODO: request RESEND when error occurs?
+    uint8_t error = PS2_USART_ERROR;  // USART error should be read before data
+    uint8_t data  = PS2_USART_RX_DATA;
+    if (!error) {
+        pbuf_enqueue(data);
+    } else {
+        xprintf("PS2 USART error: %02X data: %02X\n", error, data);
+    }
+}
+/* send LED state to keyboard */
+void ps2_host_set_led(uint8_t led) {
+    ps2_host_send(0xED);
+    ps2_host_send(led);
+}
+/*--------------------------------------------------------------------
+ * Ring buffer to store scan codes from keyboard
+ *------------------------------------------------------------------*/
+#define PBUF_SIZE 32
+static uint8_t     pbuf[PBUF_SIZE];
+static uint8_t     pbuf_head = 0;
+static uint8_t     pbuf_tail = 0;
+static inline void pbuf_enqueue(uint8_t data) {
+    uint8_t sreg = SREG;
+    cli();
+    uint8_t next = (pbuf_head + 1) % PBUF_SIZE;
+    if (next != pbuf_tail) {
+        pbuf[pbuf_head] = data;
+        pbuf_head       = next;
+    } else {
+        print("pbuf: full\n");
+    }
+    SREG = sreg;
+}
+static inline uint8_t pbuf_dequeue(void) {
+    uint8_t val = 0;
+    uint8_t sreg = SREG;
+    cli();
+    if (pbuf_head != pbuf_tail) {
+        val       = pbuf[pbuf_tail];
+        pbuf_tail = (pbuf_tail + 1) % PBUF_SIZE;
+    }
+    SREG = sreg;
+    return val;
+}
+static inline bool pbuf_has_data(void) {
+    uint8_t sreg = SREG;
+    cli();
+    bool has_data = (pbuf_head != pbuf_tail);
+    SREG          = sreg;
+    return has_data;
+}
+static inline void pbuf_clear(void) {
+    uint8_t sreg = SREG;
+    cli();
+    pbuf_head = pbuf_tail = 0;
+    SREG                  = sreg;
+}
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
new file mode 100644
index 000000000..6c837bb8e
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
+\ No newline at end of file
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h
new file mode 100644
index 000000000..8cb771bc1
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h
@@ -0,0 +1,28 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+#define STM32_HSECLK 12000000
+// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
+#define BOARD_OTG_NOVBUSSENS
+#include_next "board.h"
+#undef STM32_HSE_BYPASS
+#undef STM32F407xx
+#define STM32F405xG
+#define STM32F405xx
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
new file mode 100644
index 000000000..cc52a953e
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
@@ -0,0 +1,23 @@
+/* Copyright 2021 Andrei Purdea
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/* Address for jumping to bootloader on STM32 chips. */
+/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
+ */
+#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
new file mode 100644
index 000000000..d2ec632d9
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
@@ -0,0 +1,355 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef MCUCONF_H
+#define MCUCONF_H
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+#define STM32F4xx_MCUCONF
+#define STM32F405_MCUCONF
+#define STM32F415_MCUCONF
+#define STM32F407_MCUCONF
+#define STM32F417_MCUCONF
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_PVD_ENABLE                    FALSE
+#define STM32_PLS                           STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE                 FALSE
+#define STM32_HSI_ENABLED                   TRUE
+#define STM32_LSI_ENABLED                   TRUE
+#define STM32_HSE_ENABLED                   TRUE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_CLOCK48_REQUIRED              TRUE
+#define STM32_SW                            STM32_SW_PLL
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE                    12
+#define STM32_PLLN_VALUE                    336
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    7
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE1                         STM32_PPRE1_DIV4
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE                 192
+#define STM32_PLLI2SR_VALUE                 5
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY            6
+#define STM32_IRQ_EXTI1_PRIORITY            6
+#define STM32_IRQ_EXTI2_PRIORITY            6
+#define STM32_IRQ_EXTI3_PRIORITY            6
+#define STM32_IRQ_EXTI4_PRIORITY            6
+#define STM32_IRQ_EXTI5_9_PRIORITY          6
+#define STM32_IRQ_EXTI10_15_PRIORITY        6
+#define STM32_IRQ_EXTI16_PRIORITY           6
+#define STM32_IRQ_EXTI17_PRIORITY           15
+#define STM32_IRQ_EXTI18_PRIORITY           6
+#define STM32_IRQ_EXTI19_PRIORITY           6
+#define STM32_IRQ_EXTI20_PRIORITY           6
+#define STM32_IRQ_EXTI21_PRIORITY           15
+#define STM32_IRQ_EXTI22_PRIORITY           15
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_USE_ADC2                  FALSE
+#define STM32_ADC_USE_ADC3                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_ADC2_DMA_PRIORITY         2
+#define STM32_ADC_ADC3_DMA_PRIORITY         2
+#define STM32_ADC_IRQ_PRIORITY              6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1                  FALSE
+#define STM32_CAN_USE_CAN2                  FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY         11
+#define STM32_CAN_CAN2_IRQ_PRIORITY         11
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE                 FALSE
+#define STM32_DAC_USE_DAC1_CH1              FALSE
+#define STM32_DAC_USE_DAC1_CH2              FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM5                  FALSE
+#define STM32_GPT_USE_TIM6                  FALSE
+#define STM32_GPT_USE_TIM7                  FALSE
+#define STM32_GPT_USE_TIM8                  FALSE
+#define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM11                 FALSE
+#define STM32_GPT_USE_TIM12                 FALSE
+#define STM32_GPT_USE_TIM14                 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY         7
+#define STM32_GPT_TIM2_IRQ_PRIORITY         7
+#define STM32_GPT_TIM3_IRQ_PRIORITY         7
+#define STM32_GPT_TIM4_IRQ_PRIORITY         7
+#define STM32_GPT_TIM5_IRQ_PRIORITY         7
+#define STM32_GPT_TIM6_IRQ_PRIORITY         7
+#define STM32_GPT_TIM7_IRQ_PRIORITY         7
+#define STM32_GPT_TIM8_IRQ_PRIORITY         7
+#define STM32_GPT_TIM9_IRQ_PRIORITY         7
+#define STM32_GPT_TIM11_IRQ_PRIORITY        7
+#define STM32_GPT_TIM12_IRQ_PRIORITY        7
+#define STM32_GPT_TIM14_IRQ_PRIORITY        7
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_BUSY_TIMEOUT              50
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         5
+#define STM32_I2C_I2C2_IRQ_PRIORITY         5
+#define STM32_I2C_I2C3_IRQ_PRIORITY         5
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_I2C3_DMA_PRIORITY         3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2                  FALSE
+#define STM32_I2S_USE_SPI3                  FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY         10
+#define STM32_I2S_SPI3_IRQ_PRIORITY         10
+#define STM32_I2S_SPI2_DMA_PRIORITY         1
+#define STM32_I2S_SPI3_DMA_PRIORITY         1
+#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM8                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY         7
+#define STM32_ICU_TIM2_IRQ_PRIORITY         7
+#define STM32_ICU_TIM3_IRQ_PRIORITY         7
+#define STM32_ICU_TIM4_IRQ_PRIORITY         7
+#define STM32_ICU_TIM5_IRQ_PRIORITY         7
+#define STM32_ICU_TIM8_IRQ_PRIORITY         7
+#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED              FALSE
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  FALSE
+#define STM32_PWM_USE_TIM5                  FALSE
+#define STM32_PWM_USE_TIM8                  FALSE
+#define STM32_PWM_USE_TIM9                  FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY         7
+#define STM32_PWM_TIM2_IRQ_PRIORITY         7
+#define STM32_PWM_TIM3_IRQ_PRIORITY         7
+#define STM32_PWM_TIM4_IRQ_PRIORITY         7
+#define STM32_PWM_TIM5_IRQ_PRIORITY         7
+#define STM32_PWM_TIM8_IRQ_PRIORITY         7
+#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE               32
+#define STM32_RTC_PRESS_VALUE               1024
+#define STM32_RTC_CR_INIT                   0
+#define STM32_RTC_TAMPCR_INIT               0
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY         3
+#define STM32_SDC_SDIO_IRQ_PRIORITY         9
+#define STM32_SDC_WRITE_TIMEOUT_MS          1000
+#define STM32_SDC_READ_TIMEOUT_MS           1000
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
+#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             FALSE
+#define STM32_SERIAL_USE_USART3             FALSE
+#define STM32_SERIAL_USE_UART4              FALSE
+#define STM32_SERIAL_USE_UART5              FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+#define STM32_SERIAL_USART1_PRIORITY        12
+#define STM32_SERIAL_USART2_PRIORITY        12
+#define STM32_SERIAL_USART3_PRIORITY        12
+#define STM32_SERIAL_UART4_PRIORITY         12
+#define STM32_SERIAL_UART5_PRIORITY         12
+#define STM32_SERIAL_USART6_PRIORITY        12
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  FALSE
+#define STM32_SPI_USE_SPI3                  FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               8
+#define STM32_ST_USE_TIMER                  2
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART3               FALSE
+#define STM32_UART_USE_UART4                FALSE
+#define STM32_UART_USE_UART5                FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY      12
+#define STM32_UART_USART2_IRQ_PRIORITY      12
+#define STM32_UART_USART3_IRQ_PRIORITY      12
+#define STM32_UART_UART4_IRQ_PRIORITY       12
+#define STM32_UART_UART5_IRQ_PRIORITY       12
+#define STM32_UART_USART6_IRQ_PRIORITY      12
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#define STM32_UART_UART4_DMA_PRIORITY       0
+#define STM32_UART_UART5_DMA_PRIORITY       0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1                  TRUE
+#define STM32_USB_USE_OTG2                  FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#define STM32_USB_OTG2_IRQ_PRIORITY         14
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
+#define STM32_USB_HOST_WAKEUP_DURATION      2
+#define STM32_USB_OTG_THREAD_PRIO           NORMALPRIO+1
+#define STM32_USB_OTG_THREAD_STACK_SIZE     128
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG                  FALSE
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/config.h b/platforms/chibios/boards/QMK_PROTON_C/configs/config.h
index a73f0c0b4..fa1a73c35 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/config.h
+++ b/platforms/chibios/boards/QMK_PROTON_C/configs/config.h
@@ -18,3 +18,12 @@
 #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
 #    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
 #endif
+#ifdef CONVERT_TO_PROTON_C
+#    ifndef I2C1_SDA_PIN
+#        define I2C1_SDA_PIN D1
+#    endif
+#    ifndef I2C1_SCL_PIN
+#        define I2C1_SCL_PIN D0
+#    endif
+#endif
diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk b/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk
new file mode 100644
index 000000000..960fc2678
--- /dev/null
+++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
new file mode 100644
index 000000000..6e5adb0fe
--- /dev/null
+++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
@@ -0,0 +1,23 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/* To compile the ChibiOS syscall stubs with picolibc
+ * the _reent struct has to be defined. */
+#if !defined(_FROM_ASM_) && defined(USE_PICOLIBC)
+struct _reent;
+#endif
+#include_next <chconf.h>
+\ No newline at end of file
diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h
new file mode 100644
index 000000000..ab086567e
--- /dev/null
+++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h
@@ -0,0 +1,302 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#pragma once
+#define GD32VF103_MCUCONF
+#define GD32VF103CB
+/*
+ * GD32VF103 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 0...15       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+/*
+ * HAL driver system settings.
+*/
+#if defined(OVERCLOCK_120MHZ)
+/* (8MHz / 2) * 30 = 120MHz Sysclock */
+#define GD32_ALLOW_120MHZ_SYSCLK
+#define GD32_PLLMF_VALUE                     30
+#define GD32_USBFSPSC                        GD32_USBFSPSC_DIV2P5
+#else
+/* (8MHz / 2) * 24 = 96MHz Sysclock */
+#define GD32_PLLMF_VALUE                     24
+#define GD32_USBFSPSC                        GD32_USBFSPSC_DIV2
+#endif
+#define GD32_NO_INIT                         FALSE
+#define GD32_IRC8M_ENABLED                   TRUE
+#define GD32_IRC40K_ENABLED                  FALSE
+#define GD32_HXTAL_ENABLED                   TRUE
+#define GD32_LXTAL_ENABLED                   FALSE
+#define GD32_SCS                             GD32_SCS_PLL
+#define GD32_PLLSEL                          GD32_PLLSEL_PREDV0
+#define GD32_PREDV0SEL                       GD32_PREDV0SEL_HXTAL
+#define GD32_PREDV0_VALUE                    2
+#define GD32_PREDV1_VALUE                    2
+#define GD32_PLL1MF_VALUE                    14
+#define GD32_PLL2MF_VALUE                    13
+#define GD32_AHBPSC                          GD32_AHBPSC_DIV1
+#define GD32_APB1PSC                         GD32_APB1PSC_DIV2
+#define GD32_APB2PSC                         GD32_APB2PSC_DIV1
+#define GD32_ADCPSC                          GD32_ADCPSC_DIV16
+#define GD32_USB_CLOCK_REQUIRED              TRUE
+#define GD32_I2S_CLOCK_REQUIRED              FALSE
+#define GD32_CKOUT0SEL                       GD32_CKOUT0SEL_NOCLOCK
+#define GD32_RTCSRC                          GD32_RTCSRC_NOCLOCK
+#define GD32_PVD_ENABLE                      FALSE
+#define GD32_LVDT                            GD32_LVDT_LEV0
+/*
+ * ECLIC system settings.
+ */
+#define ECLIC_TRIGGER_DEFAULT                ECLIC_POSTIVE_EDGE_TRIGGER
+#define ECLIC_DMA_TRIGGER                    ECLIC_TRIGGER_DEFAULT
+/*
+ * IRQ system settings.
+ */
+#define GD32_IRQ_EXTI0_PRIORITY              6
+#define GD32_IRQ_EXTI1_PRIORITY              6
+#define GD32_IRQ_EXTI2_PRIORITY              6
+#define GD32_IRQ_EXTI3_PRIORITY              6
+#define GD32_IRQ_EXTI4_PRIORITY              6
+#define GD32_IRQ_EXTI5_9_PRIORITY            6
+#define GD32_IRQ_EXTI10_15_PRIORITY          6
+#define GD32_IRQ_EXTI0_TRIGGER               ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI1_TRIGGER               ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI2_TRIGGER               ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI3_TRIGGER               ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI4_TRIGGER               ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI5_9_TRIGGER             ECLIC_TRIGGER_DEFAULT
+#define GD32_IRQ_EXTI10_15_TRIGGER           ECLIC_TRIGGER_DEFAULT
+/*
+ * ADC driver system settings.
+ */
+#define GD32_ADC_USE_ADC0                    FALSE
+#define GD32_ADC_ADC0_DMA_PRIORITY           2
+#define GD32_ADC_ADC0_IRQ_PRIORITY           6
+/*
+ * CAN driver system settings.
+ */
+#define GD32_CAN_USE_CAN0                    FALSE
+#define GD32_CAN_CAN0_IRQ_PRIORITY           11
+#define GD32_CAN_USE_CAN1                    FALSE
+#define GD32_CAN_CAN1_IRQ_PRIORITY           11
+#define GD32_CAN_CAN0_IRQ_TRIGGER            ECLIC_TRIGGER_DEFAULT
+#define GD32_CAN_CAN1_IRQ_TRIGGER            ECLIC_TRIGGER_DEFAULT
+/*
+ * CRC driver system settings.
+ */
+#define GD32_CRC_USE_CRC0                   FALSE
+#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY      14
+#define GD32_CRC_CRC0_DMA_PRIORITY          2
+#define GD32_CRC_CRC0_DMA_STREAM            GD32_DMA_STREAM_ID(0, 0)
+#define CRC_USE_DMA                         FALSE
+#define CRCSW_USE_CRC1                      FALSE
+#define CRCSW_CRC32_TABLE                   FALSE
+#define CRCSW_CRC16_TABLE                   FALSE
+#define CRCSW_PROGRAMMABLE                  FALSE
+/*
+ * DAC driver system settings.
+ */
+#define GD32_DAC_USE_DAC_CH1                FALSE
+#define GD32_DAC_USE_DAC_CH2                FALSE
+/*
+ * GPT driver system settings.
+ */
+#define GD32_GPT_USE_TIM0                   FALSE
+#define GD32_GPT_USE_TIM1                   FALSE
+#define GD32_GPT_USE_TIM2                   FALSE
+#define GD32_GPT_USE_TIM3                   FALSE
+#define GD32_GPT_USE_TIM4                   FALSE
+#define GD32_GPT_TIM0_IRQ_PRIORITY          7
+#define GD32_GPT_TIM1_IRQ_PRIORITY          7
+#define GD32_GPT_TIM2_IRQ_PRIORITY          7
+#define GD32_GPT_TIM3_IRQ_PRIORITY          7
+#define GD32_GPT_TIM4_IRQ_PRIORITY          7
+#define GD32_GPT_TIM0_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM1_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM2_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM3_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM4_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM5_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_GPT_TIM6_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+/*
+ * I2S driver system settings.
+ */
+#define GD32_I2S_USE_SPI1                   FALSE
+#define GD32_I2S_USE_SPI2                   FALSE
+#define GD32_I2S_SPI1_IRQ_PRIORITY          10
+#define GD32_I2S_SPI2_IRQ_PRIORITY          10
+#define GD32_I2S_SPI1_DMA_PRIORITY          1
+#define GD32_I2S_SPI2_DMA_PRIORITY          1
+#define GD32_I2S_DMA_ERROR_HOOK(i2sp)       osalSysHalt("DMA failure")
+/*
+ * I2C driver system settings.
+ */
+#define GD32_I2C_USE_I2C0                   FALSE
+#define GD32_I2C_USE_I2C1                   FALSE
+#define GD32_I2C_BUSY_TIMEOUT               50
+#define GD32_I2C_I2C0_IRQ_PRIORITY          10
+#define GD32_I2C_I2C1_IRQ_PRIORITY          5
+#define GD32_I2C_I2C0_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_I2C_I2C1_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_I2C_I2C0_DMA_PRIORITY          2
+#define GD32_I2C_I2C1_DMA_PRIORITY          2
+#define GD32_I2C_DMA_ERROR_HOOK(i2cp)       osalSysHalt("DMA failure")
+/*
+ * ICU driver system settings.
+ */
+#define GD32_ICU_USE_TIM0                   FALSE
+#define GD32_ICU_USE_TIM1                   FALSE
+#define GD32_ICU_USE_TIM2                   FALSE
+#define GD32_ICU_USE_TIM3                   FALSE
+#define GD32_ICU_USE_TIM4                   FALSE
+#define GD32_ICU_TIM0_IRQ_PRIORITY          7
+#define GD32_ICU_TIM1_IRQ_PRIORITY          7
+#define GD32_ICU_TIM2_IRQ_PRIORITY          7
+#define GD32_ICU_TIM3_IRQ_PRIORITY          7
+#define GD32_ICU_TIM4_IRQ_PRIORITY          7
+#define GD32_ICU_TIM0_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_ICU_TIM1_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_ICU_TIM2_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_ICU_TIM3_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_ICU_TIM4_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+/*
+ * PWM driver system settings.
+ */
+#define GD32_PWM_USE_ADVANCED               FALSE
+#define GD32_PWM_USE_TIM0                   FALSE
+#define GD32_PWM_USE_TIM1                   FALSE
+#define GD32_PWM_USE_TIM2                   FALSE
+#define GD32_PWM_USE_TIM3                   FALSE
+#define GD32_PWM_USE_TIM4                   FALSE
+#define GD32_PWM_TIM0_IRQ_PRIORITY          10
+#define GD32_PWM_TIM1_IRQ_PRIORITY          10
+#define GD32_PWM_TIM2_IRQ_PRIORITY          10
+#define GD32_PWM_TIM3_IRQ_PRIORITY          10
+#define GD32_PWM_TIM4_IRQ_PRIORITY          10
+#define GD32_PWM_TIM0_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_PWM_TIM1_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_PWM_TIM2_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_PWM_TIM3_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_PWM_TIM4_IRQ_TRIGGER           ECLIC_TRIGGER_DEFAULT
+/*
+ * RTC driver system settings.
+ */
+#define GD32_RTC_IRQ_PRIORITY               15
+#define GD32_RTC_IRQ_TRIGGER                ECLIC_TRIGGER_DEFAULT
+/*
+ * SERIAL driver system settings.
+ */
+#define GD32_SERIAL_USE_USART0              FALSE
+#define GD32_SERIAL_USE_USART1              FALSE
+#define GD32_SERIAL_USE_USART2              FALSE
+#define GD32_SERIAL_USE_UART3               FALSE
+#define GD32_SERIAL_USE_UART4               FALSE
+#define GD32_SERIAL_USART0_PRIORITY         10
+#define GD32_SERIAL_USART1_PRIORITY         10
+#define GD32_SERIAL_USART2_PRIORITY         10
+#define GD32_SERIAL_UART3_PRIORITY          10
+#define GD32_SERIAL_UART4_PRIORITY          10
+#define GD32_SERIAL_USART0_TRIGGER          ECLIC_TRIGGER_DEFAULT
+#define GD32_SERIAL_USART1_TRIGGER          ECLIC_TRIGGER_DEFAULT
+#define GD32_SERIAL_USART2_TRIGGER          ECLIC_TRIGGER_DEFAULT
+#define GD32_SERIAL_UART3_TRIGGER           ECLIC_TRIGGER_DEFAULT
+#define GD32_SERIAL_UART4_TRIGGER           ECLIC_TRIGGER_DEFAULT
+/*
+ * SPI driver system settings.
+ */
+#define GD32_SPI_USE_SPI0                   FALSE
+#define GD32_SPI_USE_SPI1                   FALSE
+#define GD32_SPI_USE_SPI2                   FALSE
+#define GD32_SPI_SPI0_DMA_PRIORITY          1
+#define GD32_SPI_SPI1_DMA_PRIORITY          1
+#define GD32_SPI_SPI2_DMA_PRIORITY          1
+#define GD32_SPI_SPI0_IRQ_PRIORITY          10
+#define GD32_SPI_SPI1_IRQ_PRIORITY          10
+#define GD32_SPI_SPI2_IRQ_PRIORITY          10
+#define GD32_SPI_DMA_ERROR_HOOK(spip)       osalSysHalt("DMA failure")
+/*
+ * ST driver system settings.
+ */
+#define GD32_ST_IRQ_PRIORITY                10
+#define GD32_ST_IRQ_TRIGGER                 ECLIC_TRIGGER_DEFAULT
+#define GD32_ST_USE_TIMER                   1
+/*
+ * UART driver system settings.
+ */
+#define GD32_UART_USE_USART0                FALSE
+#define GD32_UART_USE_USART1                FALSE
+#define GD32_UART_USE_USART2                FALSE
+#define GD32_UART_USE_UART3                 FALSE
+#define GD32_UART_USE_UART4                 FALSE
+#define GD32_UART_USART0_IRQ_PRIORITY       10
+#define GD32_UART_USART1_IRQ_PRIORITY       10
+#define GD32_UART_USART2_IRQ_PRIORITY       10
+#define GD32_UART_UART3_IRQ_PRIORITY        10
+#define GD32_UART_UART4_IRQ_PRIORITY        10
+#define GD32_UART_USART0_IRQ_TRIGGER        ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_USART1_IRQ_TRIGGER        ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_USART2_IRQ_TRIGGER        ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_UART3_IRQ_TRIGGER         ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_UART4_IRQ_TRIGGER         ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_USART0_DMA_PRIORITY       3
+#define GD32_UART_USART1_DMA_PRIORITY       3
+#define GD32_UART_USART2_DMA_PRIORITY       3
+#define GD32_UART_UART3_DMA_PRIORITY        3
+#define GD32_UART_UART4_DMA_PRIORITY        3
+#define GD32_UART_DMA_ERROR_HOOK(uartp)     osalSysHalt("DMA failure")
+/*
+ * USB driver system settings.
+ */
+#define GD32_USB_USE_USBFS                  TRUE
+#define GD32_USB_USBFS_IRQ_PRIORITY         10
+#define GD32_USB_USBFS_IRQ_TRIGGER          ECLIC_TRIGGER_DEFAULT
+#define GD32_USB_USBFS_RX_FIFO_SIZE         256
+/*
+ * WDG driver system settings.
+ */
+#define GD32_WDG_USE_FWDGT                  FALSE
diff --git a/platforms/chibios/boards/common/ld/STM32F401xC.ld b/platforms/chibios/boards/common/ld/STM32F401xC.ld
new file mode 100644
index 000000000..8fae66cec
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F401xC.ld
@@ -0,0 +1,85 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * STM32F401xC memory setup.
+ */
+MEMORY
+{
+    flash0 (rx) : org = 0x08000000, len = 16k        /* Sector 0    - Init code as ROM bootloader assumes application starts here */
+    flash1 (rx) : org = 0x08004000, len = 16k        /* Sector 1    - Emulated eeprom */
+    flash2 (rx) : org = 0x08008000, len = 256k - 32k /* Sector 2..6 - Rest of firmware */
+    flash3 (rx) : org = 0x00000000, len = 0
+    flash4 (rx) : org = 0x00000000, len = 0
+    flash5 (rx) : org = 0x00000000, len = 0
+    flash6 (rx) : org = 0x00000000, len = 0
+    flash7 (rx) : org = 0x00000000, len = 0
+    ram0   (wx) : org = 0x20000000, len = 64k
+    ram1   (wx) : org = 0x00000000, len = 0
+    ram2   (wx) : org = 0x00000000, len = 0
+    ram3   (wx) : org = 0x00000000, len = 0
+    ram4   (wx) : org = 0x00000000, len = 0
+    ram5   (wx) : org = 0x00000000, len = 0
+    ram6   (wx) : org = 0x00000000, len = 0
+    ram7   (wx) : org = 0x00000000, len = 0
+}
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F401xE.ld b/platforms/chibios/boards/common/ld/STM32F401xE.ld
new file mode 100644
index 000000000..69af7ed71
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F401xE.ld
@@ -0,0 +1,85 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * STM32F401xE memory setup.
+ */
+MEMORY
+{
+    flash0 (rx) : org = 0x08000000, len = 16k        /* Sector 0    - Init code as ROM bootloader assumes application starts here */
+    flash1 (rx) : org = 0x08004000, len = 16k        /* Sector 1    - Emulated eeprom */
+    flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
+    flash3 (rx) : org = 0x00000000, len = 0
+    flash4 (rx) : org = 0x00000000, len = 0
+    flash5 (rx) : org = 0x00000000, len = 0
+    flash6 (rx) : org = 0x00000000, len = 0
+    flash7 (rx) : org = 0x00000000, len = 0
+    ram0   (wx) : org = 0x20000000, len = 96k
+    ram1   (wx) : org = 0x00000000, len = 0
+    ram2   (wx) : org = 0x00000000, len = 0
+    ram3   (wx) : org = 0x00000000, len = 0
+    ram4   (wx) : org = 0x00000000, len = 0
+    ram5   (wx) : org = 0x00000000, len = 0
+    ram6   (wx) : org = 0x00000000, len = 0
+    ram7   (wx) : org = 0x00000000, len = 0
+}
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F405xG.ld b/platforms/chibios/boards/common/ld/STM32F405xG.ld
new file mode 100644
index 000000000..b7d0baa21
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F405xG.ld
@@ -0,0 +1,86 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * STM32F405xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+    flash0 (rx) : org = 0x08000000, len = 16k      /* Sector 0    - Init code as ROM bootloader assumes application starts here */
+    flash1 (rx) : org = 0x08004000, len = 16k      /* Sector 1    - Emulated eeprom */
+    flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */
+    flash3 (rx) : org = 0x00000000, len = 0
+    flash4 (rx) : org = 0x00000000, len = 0
+    flash5 (rx) : org = 0x00000000, len = 0
+    flash6 (rx) : org = 0x00000000, len = 0
+    flash7 (rx) : org = 0x00000000, len = 0
+    ram0   (wx) : org = 0x20000000, len = 128k      /* SRAM1 + SRAM2 */
+    ram1   (wx) : org = 0x20000000, len = 112k      /* SRAM1 */
+    ram2   (wx) : org = 0x2001C000, len = 16k       /* SRAM2 */
+    ram3   (wx) : org = 0x00000000, len = 0
+    ram4   (wx) : org = 0x10000000, len = 64k       /* CCM SRAM */
+    ram5   (wx) : org = 0x40024000, len = 4k        /* BCKP SRAM */
+    ram6   (wx) : org = 0x00000000, len = 0
+    ram7   (wx) : org = 0x00000000, len = 0
+}
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F411xE.ld b/platforms/chibios/boards/common/ld/STM32F411xE.ld
new file mode 100644
index 000000000..aea8084b5
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F411xE.ld
@@ -0,0 +1,85 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * STM32F411xE memory setup.
+ */
+MEMORY
+{
+    flash0 (rx) : org = 0x08000000, len = 16k        /* Sector 0    - Init code as ROM bootloader assumes application starts here */
+    flash1 (rx) : org = 0x08004000, len = 16k        /* Sector 1    - Emulated eeprom */
+    flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
+    flash3 (rx) : org = 0x00000000, len = 0
+    flash4 (rx) : org = 0x00000000, len = 0
+    flash5 (rx) : org = 0x00000000, len = 0
+    flash6 (rx) : org = 0x00000000, len = 0
+    flash7 (rx) : org = 0x00000000, len = 0
+    ram0   (wx) : org = 0x20000000, len = 128k
+    ram1   (wx) : org = 0x00000000, len = 0
+    ram2   (wx) : org = 0x00000000, len = 0
+    ram3   (wx) : org = 0x00000000, len = 0
+    ram4   (wx) : org = 0x00000000, len = 0
+    ram5   (wx) : org = 0x00000000, len = 0
+    ram6   (wx) : org = 0x00000000, len = 0
+    ram7   (wx) : org = 0x00000000, len = 0
+}
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
index 8c476fcac..eb437665f 100644
--- a/platforms/chibios/drivers/analog.c
+++ b/platforms/chibios/drivers/analog.c
@@ -38,7 +38,7 @@
 // Otherwise assume V3
 #if defined(STM32F0XX) || defined(STM32L0XX)
 #    define USE_ADCV1
-#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX)
+#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103)
 #    define USE_ADCV2
 #endif
@@ -75,7 +75,7 @@
 /* User configurable ADC options */
 #ifndef ADC_COUNT
-#    if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX)
+#    if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103)
 #        define ADC_COUNT 1
 #    elif defined(STM32F3XX)
 #        define ADC_COUNT 4
@@ -122,8 +122,8 @@ static ADCConversionGroup adcConversionGroup = {
    .cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
    .smpr  = ADC_SAMPLING_RATE,
 #elif defined(USE_ADCV2)
-#    if !defined(STM32F1XX)
+#    if !defined(STM32F1XX) && !defined(GD32VF103)
-    .cr2 = ADC_CR2_SWSTART,  // F103 seem very unhappy with, F401 seems very unhappy without...
+    .cr2   = ADC_CR2_SWSTART,  // F103 seem very unhappy with, F401 seems very unhappy without...
 #    endif
    .smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
    .smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
@@ -220,7 +220,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
        case F9:  return TO_MUX( ADC_CHANNEL_IN7,  2 );
        case F10: return TO_MUX( ADC_CHANNEL_IN8,  2 );
 #    endif
-#elif defined(STM32F1XX)
+#elif defined(STM32F1XX) || defined(GD32VF103)
        case A0:  return TO_MUX( ADC_CHANNEL_IN0,  0 );
        case A1:  return TO_MUX( ADC_CHANNEL_IN1,  0 );
        case A2:  return TO_MUX( ADC_CHANNEL_IN2,  0 );
diff --git a/platforms/chibios/drivers/audio_dac.h b/platforms/chibios/drivers/audio_dac.h
new file mode 100644
index 000000000..07cd622ea
--- /dev/null
+++ b/platforms/chibios/drivers/audio_dac.h
@@ -0,0 +1,126 @@
+/* Copyright 2019 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#ifndef A4
+#    define A4 PAL_LINE(GPIOA, 4)
+#endif
+#ifndef A5
+#    define A5 PAL_LINE(GPIOA, 5)
+#endif
+/**
+ * Size of the dac_buffer arrays. All must be the same size.
+ */
+#define AUDIO_DAC_BUFFER_SIZE 256U
+/**
+ * Highest value allowed sample value.
+ * since the DAC is limited to 12 bit, the absolute max is 0xfff = 4095U;
+ * lower values adjust the peak-voltage aka volume down.
+ * adjusting this value has only an effect on a sample-buffer whose values are
+ * are NOT pregenerated - see square-wave
+ */
+#ifndef AUDIO_DAC_SAMPLE_MAX
+#    define AUDIO_DAC_SAMPLE_MAX 4095U
+#endif
+#if !defined(AUDIO_DAC_SAMPLE_RATE) && !defined(AUDIO_MAX_SIMULTANEOUS_TONES) && !defined(AUDIO_DAC_QUALITY_VERY_LOW) && !defined(AUDIO_DAC_QUALITY_LOW) && !defined(AUDIO_DAC_QUALITY_HIGH) && !defined(AUDIO_DAC_QUALITY_VERY_HIGH)
+#    define AUDIO_DAC_QUALITY_SANE_MINIMUM
+#endif
+/**
+ * These presets allow you to quickly switch between quality settings for
+ * the DAC. The sample rate and maximum number of simultaneous tones roughly
+ * has an inverse relationship - slightly higher sample rates may be possible.
+ *
+ * NOTE: a high sample-rate results in a higher cpu-load, which might lead to
+ *       (audible) discontinuities and/or starve other processes of cpu-time
+ *       (like RGB-led back-lighting, ...)
+ */
+#ifdef AUDIO_DAC_QUALITY_VERY_LOW
+#    define AUDIO_DAC_SAMPLE_RATE 11025U
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 8
+#endif
+#ifdef AUDIO_DAC_QUALITY_LOW
+#    define AUDIO_DAC_SAMPLE_RATE 22050U
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 4
+#endif
+#ifdef AUDIO_DAC_QUALITY_HIGH
+#    define AUDIO_DAC_SAMPLE_RATE 44100U
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 2
+#endif
+#ifdef AUDIO_DAC_QUALITY_VERY_HIGH
+#    define AUDIO_DAC_SAMPLE_RATE 88200U
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 1
+#endif
+#ifdef AUDIO_DAC_QUALITY_SANE_MINIMUM
+/* a sane-minimum config: with a trade-off between cpu-load and tone-range
+ *
+ * the (currently) highest defined note is NOTE_B8 with 7902Hz; if we now
+ * aim for an even even multiple of the buffer-size, we end up with:
+ * ( roundUptoPow2(highest note / AUDIO_DAC_BUFFER_SIZE) * nyquist-rate * AUDIO_DAC_BUFFER_SIZE)
+ *                              7902/256 = 30.867        *       2      * 256 ~= 16384
+ * which works out (but the 'scope shows some sampling artifacts with lower harmonics :-P)
+ */
+#    define AUDIO_DAC_SAMPLE_RATE 16384U
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 8
+#endif
+/**
+ * Effective bit-rate of the DAC. 44.1khz is the standard for most audio - any
+ * lower will sacrifice perceptible audio quality. Any higher will limit the
+ * number of simultaneous tones. In most situations, a tenth (1/10) of the
+ * sample rate is where notes become unbearable.
+ */
+#ifndef AUDIO_DAC_SAMPLE_RATE
+#    define AUDIO_DAC_SAMPLE_RATE 44100U
+#endif
+/**
+ * The number of tones that can be played simultaneously. If too high a value
+ * is used here, the keyboard will freeze and glitch-out when that many tones
+ * are being played.
+ */
+#ifndef AUDIO_MAX_SIMULTANEOUS_TONES
+#    define AUDIO_MAX_SIMULTANEOUS_TONES 2
+#endif
+/**
+ * The default value of the DAC when not playing anything. Certain hardware
+ * setups may require a high (AUDIO_DAC_SAMPLE_MAX) or low (0) value here.
+ * Since multiple added sine waves tend to oscillate around the midpoint,
+ * and possibly never/rarely reach either 0 of MAX, 1/2 MAX can be a
+ * reasonable default value.
+ */
+#ifndef AUDIO_DAC_OFF_VALUE
+#    define AUDIO_DAC_OFF_VALUE AUDIO_DAC_SAMPLE_MAX / 2
+#endif
+#if AUDIO_DAC_OFF_VALUE > AUDIO_DAC_SAMPLE_MAX
+#    error "AUDIO_DAC: OFF_VALUE may not be larger than SAMPLE_MAX"
+#endif
+/**
+ *user overridable sample generation/processing
+ */
+uint16_t dac_value_generate(void);
diff --git a/platforms/chibios/drivers/audio_dac_additive.c b/platforms/chibios/drivers/audio_dac_additive.c
new file mode 100644
index 000000000..db304adb8
--- /dev/null
+++ b/platforms/chibios/drivers/audio_dac_additive.c
@@ -0,0 +1,335 @@
+/* Copyright 2016-2019 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "audio.h"
+#include <ch.h>
+#include <hal.h>
+/*
+  Audio Driver: DAC
+  which utilizes the dac unit many STM32 are equipped with, to output a modulated waveform from samples stored in the dac_buffer_* array who are passed to the hardware through DMA
+  it is also possible to have a custom sample-LUT by implementing/overriding 'dac_value_generate'
+  this driver allows for multiple simultaneous tones to be played through one single channel by doing additive wave-synthesis
+*/
+#if !defined(AUDIO_PIN)
+#    error "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under 'ARM (DAC additive)' for available options."
+#endif
+#if defined(AUDIO_PIN_ALT) && !defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+#    pragma message "Audio feature: AUDIO_PIN_ALT set, but not AUDIO_PIN_ALT_AS_NEGATIVE - pin will be left unused; audio might still work though."
+#endif
+#if !defined(AUDIO_PIN_ALT)
+// no ALT pin defined is valid, but the c-ifs below need some value set
+#    define AUDIO_PIN_ALT PAL_NOLINE
+#endif
+#if !defined(AUDIO_DAC_SAMPLE_WAVEFORM_SINE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID)
+#    define AUDIO_DAC_SAMPLE_WAVEFORM_SINE
+#endif
+#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_SINE
+/* one full sine wave over [0,2*pi], but shifted up one amplitude and left pi/4; for the samples to start at 0
+ */
+static const dacsample_t dac_buffer_sine[AUDIO_DAC_BUFFER_SIZE] = {
+    // 256 values, max 4095
+    0x0,   0x1,   0x2,   0x6,   0xa,   0xf,   0x16,  0x1e,  0x27,  0x32,  0x3d,  0x4a,  0x58,  0x67,  0x78,  0x89,  0x9c,  0xb0,  0xc5,  0xdb,  0xf2,  0x10a, 0x123, 0x13e, 0x159, 0x175, 0x193, 0x1b1, 0x1d1, 0x1f1, 0x212, 0x235, 0x258, 0x27c, 0x2a0, 0x2c6, 0x2ed, 0x314, 0x33c, 0x365, 0x38e, 0x3b8, 0x3e3, 0x40e, 0x43a, 0x467, 0x494, 0x4c2, 0x4f0, 0x51f, 0x54e, 0x57d, 0x5ad, 0x5dd, 0x60e, 0x63f, 0x670, 0x6a1, 0x6d3, 0x705, 0x737, 0x769, 0x79b, 0x7cd, 0x800, 0x832, 0x864, 0x896, 0x8c8, 0x8fa, 0x92c, 0x95e, 0x98f, 0x9c0, 0x9f1, 0xa22, 0xa52, 0xa82, 0xab1, 0xae0, 0xb0f, 0xb3d, 0xb6b, 0xb98, 0xbc5, 0xbf1, 0xc1c, 0xc47, 0xc71, 0xc9a, 0xcc3, 0xceb, 0xd12, 0xd39, 0xd5f, 0xd83, 0xda7, 0xdca, 0xded, 0xe0e, 0xe2e, 0xe4e, 0xe6c, 0xe8a, 0xea6, 0xec1, 0xedc, 0xef5, 0xf0d, 0xf24, 0xf3a, 0xf4f, 0xf63, 0xf76, 0xf87, 0xf98, 0xfa7, 0xfb5, 0xfc2, 0xfcd, 0xfd8, 0xfe1, 0xfe9, 0xff0, 0xff5, 0xff9, 0xffd, 0xffe,
+    0xfff, 0xffe, 0xffd, 0xff9, 0xff5, 0xff0, 0xfe9, 0xfe1, 0xfd8, 0xfcd, 0xfc2, 0xfb5, 0xfa7, 0xf98, 0xf87, 0xf76, 0xf63, 0xf4f, 0xf3a, 0xf24, 0xf0d, 0xef5, 0xedc, 0xec1, 0xea6, 0xe8a, 0xe6c, 0xe4e, 0xe2e, 0xe0e, 0xded, 0xdca, 0xda7, 0xd83, 0xd5f, 0xd39, 0xd12, 0xceb, 0xcc3, 0xc9a, 0xc71, 0xc47, 0xc1c, 0xbf1, 0xbc5, 0xb98, 0xb6b, 0xb3d, 0xb0f, 0xae0, 0xab1, 0xa82, 0xa52, 0xa22, 0x9f1, 0x9c0, 0x98f, 0x95e, 0x92c, 0x8fa, 0x8c8, 0x896, 0x864, 0x832, 0x800, 0x7cd, 0x79b, 0x769, 0x737, 0x705, 0x6d3, 0x6a1, 0x670, 0x63f, 0x60e, 0x5dd, 0x5ad, 0x57d, 0x54e, 0x51f, 0x4f0, 0x4c2, 0x494, 0x467, 0x43a, 0x40e, 0x3e3, 0x3b8, 0x38e, 0x365, 0x33c, 0x314, 0x2ed, 0x2c6, 0x2a0, 0x27c, 0x258, 0x235, 0x212, 0x1f1, 0x1d1, 0x1b1, 0x193, 0x175, 0x159, 0x13e, 0x123, 0x10a, 0xf2,  0xdb,  0xc5,  0xb0,  0x9c,  0x89,  0x78,  0x67,  0x58,  0x4a,  0x3d,  0x32,  0x27,  0x1e,  0x16,  0xf,   0xa,   0x6,   0x2,   0x1};
+#endif  // AUDIO_DAC_SAMPLE_WAVEFORM_SINE
+#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE
+static const dacsample_t dac_buffer_triangle[AUDIO_DAC_BUFFER_SIZE] = {
+    // 256 values, max 4095
+    0x0,   0x20,  0x40,  0x60,  0x80,  0xa0,  0xc0,  0xe0,  0x100, 0x120, 0x140, 0x160, 0x180, 0x1a0, 0x1c0, 0x1e0, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0x400, 0x420, 0x440, 0x460, 0x480, 0x4a0, 0x4c0, 0x4e0, 0x500, 0x520, 0x540, 0x560, 0x580, 0x5a0, 0x5c0, 0x5e0, 0x600, 0x620, 0x640, 0x660, 0x680, 0x6a0, 0x6c0, 0x6e0, 0x700, 0x720, 0x740, 0x760, 0x780, 0x7a0, 0x7c0, 0x7e0, 0x800, 0x81f, 0x83f, 0x85f, 0x87f, 0x89f, 0x8bf, 0x8df, 0x8ff, 0x91f, 0x93f, 0x95f, 0x97f, 0x99f, 0x9bf, 0x9df, 0x9ff, 0xa1f, 0xa3f, 0xa5f, 0xa7f, 0xa9f, 0xabf, 0xadf, 0xaff, 0xb1f, 0xb3f, 0xb5f, 0xb7f, 0xb9f, 0xbbf, 0xbdf, 0xbff, 0xc1f, 0xc3f, 0xc5f, 0xc7f, 0xc9f, 0xcbf, 0xcdf, 0xcff, 0xd1f, 0xd3f, 0xd5f, 0xd7f, 0xd9f, 0xdbf, 0xddf, 0xdff, 0xe1f, 0xe3f, 0xe5f, 0xe7f, 0xe9f, 0xebf, 0xedf, 0xeff, 0xf1f, 0xf3f, 0xf5f, 0xf7f, 0xf9f, 0xfbf, 0xfdf,
+    0xfff, 0xfdf, 0xfbf, 0xf9f, 0xf7f, 0xf5f, 0xf3f, 0xf1f, 0xeff, 0xedf, 0xebf, 0xe9f, 0xe7f, 0xe5f, 0xe3f, 0xe1f, 0xdff, 0xddf, 0xdbf, 0xd9f, 0xd7f, 0xd5f, 0xd3f, 0xd1f, 0xcff, 0xcdf, 0xcbf, 0xc9f, 0xc7f, 0xc5f, 0xc3f, 0xc1f, 0xbff, 0xbdf, 0xbbf, 0xb9f, 0xb7f, 0xb5f, 0xb3f, 0xb1f, 0xaff, 0xadf, 0xabf, 0xa9f, 0xa7f, 0xa5f, 0xa3f, 0xa1f, 0x9ff, 0x9df, 0x9bf, 0x99f, 0x97f, 0x95f, 0x93f, 0x91f, 0x8ff, 0x8df, 0x8bf, 0x89f, 0x87f, 0x85f, 0x83f, 0x81f, 0x800, 0x7e0, 0x7c0, 0x7a0, 0x780, 0x760, 0x740, 0x720, 0x700, 0x6e0, 0x6c0, 0x6a0, 0x680, 0x660, 0x640, 0x620, 0x600, 0x5e0, 0x5c0, 0x5a0, 0x580, 0x560, 0x540, 0x520, 0x500, 0x4e0, 0x4c0, 0x4a0, 0x480, 0x460, 0x440, 0x420, 0x400, 0x3e0, 0x3c0, 0x3a0, 0x380, 0x360, 0x340, 0x320, 0x300, 0x2e0, 0x2c0, 0x2a0, 0x280, 0x260, 0x240, 0x220, 0x200, 0x1e0, 0x1c0, 0x1a0, 0x180, 0x160, 0x140, 0x120, 0x100, 0xe0,  0xc0,  0xa0,  0x80,  0x60,  0x40,  0x20};
+#endif  // AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE
+#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE
+static const dacsample_t dac_buffer_square[AUDIO_DAC_BUFFER_SIZE] = {
+    [0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1]                     = 0,                     // first and
+    [AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = AUDIO_DAC_SAMPLE_MAX,  // second half
+};
+#endif  // AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE
+/*
+// four steps: 0, 1/3, 2/3 and 1
+static const dacsample_t dac_buffer_staircase[AUDIO_DAC_BUFFER_SIZE] = {
+    [0 ... AUDIO_DAC_BUFFER_SIZE/3 -1 ]                               = 0,
+    [AUDIO_DAC_BUFFER_SIZE / 4 ... AUDIO_DAC_BUFFER_SIZE / 2 -1 ]     = AUDIO_DAC_SAMPLE_MAX / 3,
+    [AUDIO_DAC_BUFFER_SIZE / 2 ... 3 * AUDIO_DAC_BUFFER_SIZE / 4 -1 ] = 2 * AUDIO_DAC_SAMPLE_MAX / 3,
+    [3 * AUDIO_DAC_BUFFER_SIZE / 4 ... AUDIO_DAC_BUFFER_SIZE -1 ]     = AUDIO_DAC_SAMPLE_MAX,
+}
+*/
+#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID
+static const dacsample_t dac_buffer_trapezoid[AUDIO_DAC_BUFFER_SIZE] = {0x0,   0x1f,  0x7f,  0xdf,  0x13f, 0x19f, 0x1ff, 0x25f, 0x2bf, 0x31f, 0x37f, 0x3df, 0x43f, 0x49f, 0x4ff, 0x55f, 0x5bf, 0x61f, 0x67f, 0x6df, 0x73f, 0x79f, 0x7ff, 0x85f, 0x8bf, 0x91f, 0x97f, 0x9df, 0xa3f, 0xa9f, 0xaff, 0xb5f, 0xbbf, 0xc1f, 0xc7f, 0xcdf, 0xd3f, 0xd9f, 0xdff, 0xe5f, 0xebf, 0xf1f, 0xf7f, 0xfdf, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff,
+                                                                        0xfff, 0xfdf, 0xf7f, 0xf1f, 0xebf, 0xe5f, 0xdff, 0xd9f, 0xd3f, 0xcdf, 0xc7f, 0xc1f, 0xbbf, 0xb5f, 0xaff, 0xa9f, 0xa3f, 0x9df, 0x97f, 0x91f, 0x8bf, 0x85f, 0x7ff, 0x79f, 0x73f, 0x6df, 0x67f, 0x61f, 0x5bf, 0x55f, 0x4ff, 0x49f, 0x43f, 0x3df, 0x37f, 0x31f, 0x2bf, 0x25f, 0x1ff, 0x19f, 0x13f, 0xdf,  0x7f,  0x1f,  0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0,   0x0};
+#endif  // AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID
+static dacsample_t dac_buffer_empty[AUDIO_DAC_BUFFER_SIZE] = {AUDIO_DAC_OFF_VALUE};
+/* keep track of the sample position for for each frequency */
+static float dac_if[AUDIO_MAX_SIMULTANEOUS_TONES] = {0.0};
+static float   active_tones_snapshot[AUDIO_MAX_SIMULTANEOUS_TONES] = {0, 0};
+static uint8_t active_tones_snapshot_length                        = 0;
+typedef enum {
+    OUTPUT_SHOULD_START,
+    OUTPUT_RUN_NORMALLY,
+    // path 1: wait for zero, then change/update active tones
+    OUTPUT_TONES_CHANGED,
+    OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE,
+    // path 2: hardware should stop, wait for zero then turn output off = stop the timer
+    OUTPUT_SHOULD_STOP,
+    OUTPUT_REACHED_ZERO_BEFORE_OFF,
+    OUTPUT_OFF,
+    OUTPUT_OFF_1,
+    OUTPUT_OFF_2,  // trailing off: giving the DAC two more conversion cycles until the AUDIO_DAC_OFF_VALUE reaches the output, then turn the timer off, which leaves the output at that level
+    number_of_output_states
+} output_states_t;
+output_states_t state = OUTPUT_OFF_2;
+/**
+ * Generation of the waveform being passed to the callback. Declared weak so users
+ * can override it with their own wave-forms/noises.
+ */
+__attribute__((weak)) uint16_t dac_value_generate(void) {
+    // DAC is running/asking for values but snapshot length is zero -> must be playing a pause
+    if (active_tones_snapshot_length == 0) {
+        return AUDIO_DAC_OFF_VALUE;
+    }
+    /* doing additive wave synthesis over all currently playing tones = adding up
+     * sine-wave-samples for each frequency, scaled by the number of active tones
+     */
+    uint16_t value     = 0;
+    float    frequency = 0.0f;
+    for (uint8_t i = 0; i < active_tones_snapshot_length; i++) {
+        /* Note: a user implementation does not have to rely on the active_tones_snapshot, but
+         * could directly query the active frequencies through audio_get_processed_frequency */
+        frequency = active_tones_snapshot[i];
+        dac_if[i] = dac_if[i] + ((frequency * AUDIO_DAC_BUFFER_SIZE) / AUDIO_DAC_SAMPLE_RATE) * 2 / 3;
+        /*Note: the 2/3 are necessary to get the correct frequencies on the
+         *      DAC output (as measured with an oscilloscope), since the gpt
+         *      timer runs with 3*AUDIO_DAC_SAMPLE_RATE; and the DAC callback
+         *      is called twice per conversion.*/
+        dac_if[i] = fmod(dac_if[i], AUDIO_DAC_BUFFER_SIZE);
+        // Wavetable generation/lookup
+        uint16_t dac_i = (uint16_t)dac_if[i];
+#if defined(AUDIO_DAC_SAMPLE_WAVEFORM_SINE)
+        value += dac_buffer_sine[dac_i] / active_tones_snapshot_length;
+#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE)
+        value += dac_buffer_triangle[dac_i] / active_tones_snapshot_length;
+#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID)
+        value += dac_buffer_trapezoid[dac_i] / active_tones_snapshot_length;
+#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE)
+        value += dac_buffer_square[dac_i] / active_tones_snapshot_length;
+#endif
+        /*
+        // SINE
+        value += dac_buffer_sine[dac_i] / active_tones_snapshot_length / 3;
+        // TRIANGLE
+        value += dac_buffer_triangle[dac_i] / active_tones_snapshot_length / 3;
+        // SQUARE
+        value += dac_buffer_square[dac_i] / active_tones_snapshot_length / 3;
+        //NOTE: combination of these three wave-forms is more exemplary - and doesn't sound particularly good :-P
+        */
+        // STAIRS (mostly usefully as test-pattern)
+        // value_avg = dac_buffer_staircase[dac_i] / active_tones_snapshot_length;
+    }
+    return value;
+}
+/**
+ * DAC streaming callback. Does all of the main computing for playing songs.
+ *
+ * Note: chibios calls this CB twice: during the 'half buffer event', and the 'full buffer event'.
+ */
+static void dac_end(DACDriver *dacp) {
+    dacsample_t *sample_p = (dacp)->samples;
+    // work on the other half of the buffer
+    if (dacIsBufferComplete(dacp)) {
+        sample_p += AUDIO_DAC_BUFFER_SIZE / 2;  // 'half_index'
+    }
+    for (uint8_t s = 0; s < AUDIO_DAC_BUFFER_SIZE / 2; s++) {
+        if (OUTPUT_OFF <= state) {
+            sample_p[s] = AUDIO_DAC_OFF_VALUE;
+            continue;
+        } else {
+            sample_p[s] = dac_value_generate();
+        }
+        /* zero crossing (or approach, whereas zero == DAC_OFF_VALUE, which can be configured to anything from 0 to DAC_SAMPLE_MAX)
+         * ============================*=*========================== AUDIO_DAC_SAMPLE_MAX
+         *                          *       *
+         *                        *           *
+         * ---------------------------------------------------------
+         *                     *                 *                  } AUDIO_DAC_SAMPLE_MAX/100
+         * --------------------------------------------------------- AUDIO_DAC_OFF_VALUE
+         *                  *                       *               } AUDIO_DAC_SAMPLE_MAX/100
+         * ---------------------------------------------------------
+         *               *
+         * *           *
+         *   *       *
+         * =====*=*================================================= 0x0
+         */
+        if (((sample_p[s] + (AUDIO_DAC_SAMPLE_MAX / 100)) > AUDIO_DAC_OFF_VALUE) &&  // value approaches from below
+            (sample_p[s] < (AUDIO_DAC_OFF_VALUE + (AUDIO_DAC_SAMPLE_MAX / 100)))     // or above
+        ) {
+            if ((OUTPUT_SHOULD_START == state) && (active_tones_snapshot_length > 0)) {
+                state = OUTPUT_RUN_NORMALLY;
+            } else if (OUTPUT_TONES_CHANGED == state) {
+                state = OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE;
+            } else if (OUTPUT_SHOULD_STOP == state) {
+                state = OUTPUT_REACHED_ZERO_BEFORE_OFF;
+            }
+        }
+        // still 'ramping up', reset the output to OFF_VALUE until the generated values reach that value, to do a smooth handover
+        if (OUTPUT_SHOULD_START == state) {
+            sample_p[s] = AUDIO_DAC_OFF_VALUE;
+        }
+        if ((OUTPUT_SHOULD_START == state) || (OUTPUT_REACHED_ZERO_BEFORE_OFF == state) || (OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE == state)) {
+            uint8_t active_tones         = MIN(AUDIO_MAX_SIMULTANEOUS_TONES, audio_get_number_of_active_tones());
+            active_tones_snapshot_length = 0;
+            // update the snapshot - once, and only on occasion that something changed;
+            // -> saves cpu cycles (?)
+            for (uint8_t i = 0; i < active_tones; i++) {
+                float freq = audio_get_processed_frequency(i);
+                if (freq > 0) {  // disregard 'rest' notes, with valid frequency 0.0f; which would only lower the resulting waveform volume during the additive synthesis step
+                    active_tones_snapshot[active_tones_snapshot_length++] = freq;
+                }
+            }
+            if ((0 == active_tones_snapshot_length) && (OUTPUT_REACHED_ZERO_BEFORE_OFF == state)) {
+                state = OUTPUT_OFF;
+            }
+            if (OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE == state) {
+                state = OUTPUT_RUN_NORMALLY;
+            }
+        }
+    }
+    // update audio internal state (note position, current_note, ...)
+    if (audio_update_state()) {
+        if (OUTPUT_SHOULD_STOP != state) {
+            state = OUTPUT_TONES_CHANGED;
+        }
+    }
+    if (OUTPUT_OFF <= state) {
+        if (OUTPUT_OFF_2 == state) {
+            // stopping timer6 = stopping the DAC at whatever value it is currently pushing to the output = AUDIO_DAC_OFF_VALUE
+            gptStopTimer(&GPTD6);
+        } else {
+            state++;
+        }
+    }
+}
+static void dac_error(DACDriver *dacp, dacerror_t err) {
+    (void)dacp;
+    (void)err;
+    chSysHalt("DAC failure. halp");
+}
+static const GPTConfig gpt6cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE * 3,
+                                   .callback  = NULL,
+                                   .cr2       = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event.  */
+                                   .dier      = 0U};
+static const DACConfig dac_conf = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
+/**
+ * @note The DAC_TRG(0) here selects the Timer 6 TRGO event, which is triggered
+ * on the rising edge after 3 APB1 clock cycles, causing our gpt6cfg1.frequency
+ * to be a third of what we expect.
+ *
+ * Here are all the values for DAC_TRG (TSEL in the ref manual)
+ * TIM15_TRGO 0b011
+ * TIM2_TRGO  0b100
+ * TIM3_TRGO  0b001
+ * TIM6_TRGO  0b000
+ * TIM7_TRGO  0b010
+ * EXTI9      0b110
+ * SWTRIG     0b111
+ */
+static const DACConversionGroup dac_conv_cfg = {.num_channels = 1U, .end_cb = dac_end, .error_cb = dac_error, .trigger = DAC_TRG(0b000)};
+void audio_driver_initialize() {
+    if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
+        palSetLineMode(A4, PAL_MODE_INPUT_ANALOG);
+        dacStart(&DACD1, &dac_conf);
+    }
+    if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
+        palSetLineMode(A5, PAL_MODE_INPUT_ANALOG);
+        dacStart(&DACD2, &dac_conf);
+    }
+    /* enable the output buffer, to directly drive external loads with no additional circuitry
+     *
+     * see: AN4566 Application note: Extending the DAC performance of STM32 microcontrollers
+     * Note: Buffer-Off bit -> has to be set 0 to enable the output buffer
+     * Note: enabling the output buffer imparts an additional dc-offset of a couple mV
+     *
+     * this is done here, reaching directly into the stm32 registers since chibios has not implemented BOFF handling yet
+     * (see: chibios/os/hal/ports/STM32/todo.txt '- BOFF handling in DACv1.'
+     */
+    DACD1.params->dac->CR &= ~DAC_CR_BOFF1;
+    DACD2.params->dac->CR &= ~DAC_CR_BOFF2;
+    if (AUDIO_PIN == A4) {
+        dacStartConversion(&DACD1, &dac_conv_cfg, dac_buffer_empty, AUDIO_DAC_BUFFER_SIZE);
+    } else if (AUDIO_PIN == A5) {
+        dacStartConversion(&DACD2, &dac_conv_cfg, dac_buffer_empty, AUDIO_DAC_BUFFER_SIZE);
+    }
+    // no inverted/out-of-phase waveform (yet?), only pulling AUDIO_PIN_ALT to AUDIO_DAC_OFF_VALUE
+#if defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+    if (AUDIO_PIN_ALT == A4) {
+        dacPutChannelX(&DACD1, 0, AUDIO_DAC_OFF_VALUE);
+    } else if (AUDIO_PIN_ALT == A5) {
+        dacPutChannelX(&DACD2, 0, AUDIO_DAC_OFF_VALUE);
+    }
+#endif
+    gptStart(&GPTD6, &gpt6cfg1);
+}
+void audio_driver_stop(void) { state = OUTPUT_SHOULD_STOP; }
+void audio_driver_start(void) {
+    gptStartContinuous(&GPTD6, 2U);
+    for (uint8_t i = 0; i < AUDIO_MAX_SIMULTANEOUS_TONES; i++) {
+        dac_if[i]                = 0.0f;
+        active_tones_snapshot[i] = 0.0f;
+    }
+    active_tones_snapshot_length = 0;
+    state                        = OUTPUT_SHOULD_START;
+}
diff --git a/platforms/chibios/drivers/audio_dac_basic.c b/platforms/chibios/drivers/audio_dac_basic.c
new file mode 100644
index 000000000..fac651350
--- /dev/null
+++ b/platforms/chibios/drivers/audio_dac_basic.c
@@ -0,0 +1,245 @@
+/* Copyright 2016-2020 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "audio.h"
+#include "ch.h"
+#include "hal.h"
+/*
+  Audio Driver: DAC
+  which utilizes both channels of the DAC unit many STM32 are equipped with to output a modulated square-wave, from precomputed samples stored in a buffer, which is passed to the hardware through DMA
+  this driver can either be used to drive to separate speakers, wired to A4+Gnd and A5+Gnd, which allows two tones to be played simultaneously
+  OR
+  one speaker wired to A4+A5 with the AUDIO_PIN_ALT_AS_NEGATIVE define set - see docs/feature_audio
+*/
+#if !defined(AUDIO_PIN)
+#    pragma message "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under 'ARM (DAC basic)' for available options."
+// TODO: make this an 'error' instead; go through a breaking change, and add AUDIO_PIN A5 to all keyboards currently using AUDIO on STM32 based boards? - for now: set the define here
+#    define AUDIO_PIN A5
+#endif
+// check configuration for ONE speaker, connected to both DAC pins
+#if defined(AUDIO_PIN_ALT_AS_NEGATIVE) && !defined(AUDIO_PIN_ALT)
+#    error "Audio feature: AUDIO_PIN_ALT_AS_NEGATIVE set, but no pin configured as AUDIO_PIN_ALT"
+#endif
+#ifndef AUDIO_PIN_ALT
+// no ALT pin defined is valid, but the c-ifs below need some value set
+#    define AUDIO_PIN_ALT -1
+#endif
+#if !defined(AUDIO_STATE_TIMER)
+#    define AUDIO_STATE_TIMER GPTD8
+#endif
+// square-wave
+static const dacsample_t dac_buffer_1[AUDIO_DAC_BUFFER_SIZE] = {
+    // First half is max, second half is 0
+    [0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1]                     = AUDIO_DAC_SAMPLE_MAX,
+    [AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = 0,
+};
+// square-wave
+static const dacsample_t dac_buffer_2[AUDIO_DAC_BUFFER_SIZE] = {
+    // opposite of dac_buffer above
+    [0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1]                     = 0,
+    [AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = AUDIO_DAC_SAMPLE_MAX,
+};
+GPTConfig gpt6cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE,
+                      .callback  = NULL,
+                      .cr2       = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event.    */
+                      .dier      = 0U};
+GPTConfig gpt7cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE,
+                      .callback  = NULL,
+                      .cr2       = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event.    */
+                      .dier      = 0U};
+static void gpt_audio_state_cb(GPTDriver *gptp);
+GPTConfig   gptStateUpdateCfg = {.frequency = 10,
+                               .callback  = gpt_audio_state_cb,
+                               .cr2       = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event.    */
+                               .dier      = 0U};
+static const DACConfig dac_conf_ch1 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
+static const DACConfig dac_conf_ch2 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
+/**
+ * @note The DAC_TRG(0) here selects the Timer 6 TRGO event, which is triggered
+ * on the rising edge after 3 APB1 clock cycles, causing our gpt6cfg1.frequency
+ * to be a third of what we expect.
+ *
+ * Here are all the values for DAC_TRG (TSEL in the ref manual)
+ * TIM15_TRGO 0b011
+ * TIM2_TRGO  0b100
+ * TIM3_TRGO  0b001
+ * TIM6_TRGO  0b000
+ * TIM7_TRGO  0b010
+ * EXTI9      0b110
+ * SWTRIG     0b111
+ */
+static const DACConversionGroup dac_conv_grp_ch1 = {.num_channels = 1U, .trigger = DAC_TRG(0b000)};
+static const DACConversionGroup dac_conv_grp_ch2 = {.num_channels = 1U, .trigger = DAC_TRG(0b010)};
+void channel_1_start(void) {
+    gptStart(&GPTD6, &gpt6cfg1);
+    gptStartContinuous(&GPTD6, 2U);
+    palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
+}
+void channel_1_stop(void) {
+    gptStopTimer(&GPTD6);
+    palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL);
+    palSetPad(GPIOA, 4);
+}
+static float channel_1_frequency = 0.0f;
+void         channel_1_set_frequency(float freq) {
+    channel_1_frequency = freq;
+    channel_1_stop();
+    if (freq <= 0.0)  // a pause/rest has freq=0
+        return;
+    gpt6cfg1.frequency = 2 * freq * AUDIO_DAC_BUFFER_SIZE;
+    channel_1_start();
+}
+float channel_1_get_frequency(void) { return channel_1_frequency; }
+void channel_2_start(void) {
+    gptStart(&GPTD7, &gpt7cfg1);
+    gptStartContinuous(&GPTD7, 2U);
+    palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
+}
+void channel_2_stop(void) {
+    gptStopTimer(&GPTD7);
+    palSetPadMode(GPIOA, 5, PAL_MODE_OUTPUT_PUSHPULL);
+    palSetPad(GPIOA, 5);
+}
+static float channel_2_frequency = 0.0f;
+void         channel_2_set_frequency(float freq) {
+    channel_2_frequency = freq;
+    channel_2_stop();
+    if (freq <= 0.0)  // a pause/rest has freq=0
+        return;
+    gpt7cfg1.frequency = 2 * freq * AUDIO_DAC_BUFFER_SIZE;
+    channel_2_start();
+}
+float channel_2_get_frequency(void) { return channel_2_frequency; }
+static void gpt_audio_state_cb(GPTDriver *gptp) {
+    if (audio_update_state()) {
+#if defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+        // one piezo/speaker connected to both audio pins, the generated square-waves are inverted
+        channel_1_set_frequency(audio_get_processed_frequency(0));
+        channel_2_set_frequency(audio_get_processed_frequency(0));
+#else  // two separate audio outputs/speakers
+       // primary speaker on A4, optional secondary on A5
+        if (AUDIO_PIN == A4) {
+            channel_1_set_frequency(audio_get_processed_frequency(0));
+            if (AUDIO_PIN_ALT == A5) {
+                if (audio_get_number_of_active_tones() > 1) {
+                    channel_2_set_frequency(audio_get_processed_frequency(1));
+                } else {
+                    channel_2_stop();
+                }
+            }
+        }
+        // primary speaker on A5, optional secondary on A4
+        if (AUDIO_PIN == A5) {
+            channel_2_set_frequency(audio_get_processed_frequency(0));
+            if (AUDIO_PIN_ALT == A4) {
+                if (audio_get_number_of_active_tones() > 1) {
+                    channel_1_set_frequency(audio_get_processed_frequency(1));
+                } else {
+                    channel_1_stop();
+                }
+            }
+        }
+#endif
+    }
+}
+void audio_driver_initialize() {
+    if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
+        palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
+        dacStart(&DACD1, &dac_conf_ch1);
+        // initial setup of the dac-triggering timer is still required, even
+        // though it gets reconfigured and restarted later on
+        gptStart(&GPTD6, &gpt6cfg1);
+    }
+    if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
+        palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
+        dacStart(&DACD2, &dac_conf_ch2);
+        gptStart(&GPTD7, &gpt7cfg1);
+    }
+    /* enable the output buffer, to directly drive external loads with no additional circuitry
+     *
+     * see: AN4566 Application note: Extending the DAC performance of STM32 microcontrollers
+     * Note: Buffer-Off bit -> has to be set 0 to enable the output buffer
+     * Note: enabling the output buffer imparts an additional dc-offset of a couple mV
+     *
+     * this is done here, reaching directly into the stm32 registers since chibios has not implemented BOFF handling yet
+     * (see: chibios/os/hal/ports/STM32/todo.txt '- BOFF handling in DACv1.'
+     */
+    DACD1.params->dac->CR &= ~DAC_CR_BOFF1;
+    DACD2.params->dac->CR &= ~DAC_CR_BOFF2;
+    // start state-updater
+    gptStart(&AUDIO_STATE_TIMER, &gptStateUpdateCfg);
+}
+void audio_driver_stop(void) {
+    if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
+        gptStopTimer(&GPTD6);
+        // stop the ongoing conversion and put the output in a known state
+        dacStopConversion(&DACD1);
+        dacPutChannelX(&DACD1, 0, AUDIO_DAC_OFF_VALUE);
+    }
+    if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
+        gptStopTimer(&GPTD7);
+        dacStopConversion(&DACD2);
+        dacPutChannelX(&DACD2, 0, AUDIO_DAC_OFF_VALUE);
+    }
+    gptStopTimer(&AUDIO_STATE_TIMER);
+}
+void audio_driver_start(void) {
+    if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
+        dacStartConversion(&DACD1, &dac_conv_grp_ch1, (dacsample_t *)dac_buffer_1, AUDIO_DAC_BUFFER_SIZE);
+    }
+    if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
+        dacStartConversion(&DACD2, &dac_conv_grp_ch2, (dacsample_t *)dac_buffer_2, AUDIO_DAC_BUFFER_SIZE);
+    }
+    gptStartContinuous(&AUDIO_STATE_TIMER, 2U);
+}
diff --git a/platforms/chibios/drivers/audio_pwm.h b/platforms/chibios/drivers/audio_pwm.h
new file mode 100644
index 000000000..86cab916e
--- /dev/null
+++ b/platforms/chibios/drivers/audio_pwm.h
@@ -0,0 +1,40 @@
+/* Copyright 2020 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#if !defined(AUDIO_PWM_DRIVER)
+// NOTE: Timer2 seems to be used otherwise in QMK, otherwise we could default to A5 (= TIM2_CH1, with PWMD2 and alternate-function(1))
+#    define AUDIO_PWM_DRIVER PWMD1
+#endif
+#if !defined(AUDIO_PWM_CHANNEL)
+// NOTE: sticking to the STM data-sheet numbering: TIMxCH1 to TIMxCH4
+// default: STM32F303CC PA8+TIM1_CH1 -> 1
+#    define AUDIO_PWM_CHANNEL 1
+#endif
+#if !defined(AUDIO_PWM_PAL_MODE)
+// pin-alternate function: see the data-sheet for which pin needs what AF to connect to TIMx_CHy
+// default: STM32F303CC PA8+TIM1_CH1 -> 6
+#    define AUDIO_PWM_PAL_MODE 6
+#endif
+#if !defined(AUDIO_STATE_TIMER)
+// timer used to trigger updates in the audio-system, configured/enabled in chibios mcuconf.
+// Tim6 is the default for "larger" STMs, smaller ones might not have this one (enabled) and need to switch to a different one (e.g.: STM32F103 has only Tim1-Tim4)
+#    define AUDIO_STATE_TIMER GPTD6
+#endif
diff --git a/platforms/chibios/drivers/audio_pwm_hardware.c b/platforms/chibios/drivers/audio_pwm_hardware.c
new file mode 100644
index 000000000..cd40019ee
--- /dev/null
+++ b/platforms/chibios/drivers/audio_pwm_hardware.c
@@ -0,0 +1,144 @@
+/* Copyright 2020 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+Audio Driver: PWM
+the duty-cycle is always kept at 50%, and the pwm-period is adjusted to match the frequency of a note to be played back.
+this driver uses the chibios-PWM system to produce a square-wave on specific output pins that are connected to the PWM hardware.
+The hardware directly toggles the pin via its alternate function. see your MCUs data-sheet for which pin can be driven by what timer - looking for TIMx_CHy and the corresponding alternate function.
+ */
+#include "audio.h"
+#include "ch.h"
+#include "hal.h"
+#if !defined(AUDIO_PIN)
+#    error "Audio feature enabled, but no pin selected - see docs/feature_audio under the ARM PWM settings"
+#endif
+extern bool    playing_note;
+extern bool    playing_melody;
+extern uint8_t note_timbre;
+static PWMConfig pwmCFG = {
+    .frequency = 100000, /* PWM clock frequency  */
+    // CHIBIOS-BUG? can't set the initial period to <2, or the pwm (hard or software) takes ~130ms with .frequency=500000 for a pwmChangePeriod to take effect; with no output=silence in the meantime
+    .period   = 2,    /* initial PWM period (in ticks) 1S (1/10kHz=0.1mS 0.1ms*10000 ticks=1S) */
+    .callback = NULL, /* no callback, the hardware directly toggles the pin */
+    .channels =
+        {
+#if AUDIO_PWM_CHANNEL == 4
+            {PWM_OUTPUT_DISABLED, NULL},   /* channel 0 -> TIMx_CH1 */
+            {PWM_OUTPUT_DISABLED, NULL},   /* channel 1 -> TIMx_CH2 */
+            {PWM_OUTPUT_DISABLED, NULL},   /* channel 2 -> TIMx_CH3 */
+            {PWM_OUTPUT_ACTIVE_HIGH, NULL} /* channel 3 -> TIMx_CH4 */
+#elif AUDIO_PWM_CHANNEL == 3
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH3 */
+            {PWM_OUTPUT_DISABLED, NULL}
+#elif AUDIO_PWM_CHANNEL == 2
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH2 */
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_DISABLED, NULL}
+#else /*fallback to CH1 */
+            {PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH1 */
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_DISABLED, NULL},
+            {PWM_OUTPUT_DISABLED, NULL}
+#endif
+        },
+};
+static float channel_1_frequency = 0.0f;
+void         channel_1_set_frequency(float freq) {
+    channel_1_frequency = freq;
+    if (freq <= 0.0)  // a pause/rest has freq=0
+        return;
+    pwmcnt_t period = (pwmCFG.frequency / freq);
+    pwmChangePeriod(&AUDIO_PWM_DRIVER, period);
+    pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
+                     // adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
+                     PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
+}
+float channel_1_get_frequency(void) { return channel_1_frequency; }
+void channel_1_start(void) {
+    pwmStop(&AUDIO_PWM_DRIVER);
+    pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
+}
+void channel_1_stop(void) { pwmStop(&AUDIO_PWM_DRIVER); }
+static void gpt_callback(GPTDriver *gptp);
+GPTConfig   gptCFG = {
+    /* a whole note is one beat, which is - per definition in musical_notes.h - set to 64
+       the longest note is BREAVE_DOT=128+64=192, the shortest SIXTEENTH=4
+       the tempo (which might vary!) is in bpm (beats per minute)
+       therefore: if the timer ticks away at .frequency = (60*64)Hz,
+       and the .interval counts from 64 downwards - audio_update_state is
+       called just often enough to not miss any notes
+    */
+    .frequency = 60 * 64,
+    .callback  = gpt_callback,
+};
+void audio_driver_initialize(void) {
+    pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
+    // connect the AUDIO_PIN to the PWM hardware
+#if defined(USE_GPIOV1)  // STM32F103C8
+    palSetLineMode(AUDIO_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
+#else  // GPIOv2 (or GPIOv3 for f4xx, which is the same/compatible at this command)
+    palSetLineMode(AUDIO_PIN, PAL_MODE_ALTERNATE(AUDIO_PWM_PAL_MODE));
+#endif
+    gptStart(&AUDIO_STATE_TIMER, &gptCFG);
+}
+void audio_driver_start(void) {
+    channel_1_stop();
+    channel_1_start();
+    if (playing_note || playing_melody) {
+        gptStartContinuous(&AUDIO_STATE_TIMER, 64);
+    }
+}
+void audio_driver_stop(void) {
+    channel_1_stop();
+    gptStopTimer(&AUDIO_STATE_TIMER);
+}
+/* a regular timer task, that checks the note to be currently played
+ * and updates the pwm to output that frequency
+ */
+static void gpt_callback(GPTDriver *gptp) {
+    float freq;  // TODO: freq_alt
+    if (audio_update_state()) {
+        freq = audio_get_processed_frequency(0);  // freq_alt would be index=1
+        channel_1_set_frequency(freq);
+    }
+}
diff --git a/platforms/chibios/drivers/audio_pwm_software.c b/platforms/chibios/drivers/audio_pwm_software.c
new file mode 100644
index 000000000..15c3e98b6
--- /dev/null
+++ b/platforms/chibios/drivers/audio_pwm_software.c
@@ -0,0 +1,164 @@
+/* Copyright 2020 Jack Humbert
+ * Copyright 2020 JohSchneider
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+Audio Driver: PWM
+the duty-cycle is always kept at 50%, and the pwm-period is adjusted to match the frequency of a note to be played back.
+this driver uses the chibios-PWM system to produce a square-wave on any given output pin in software
+- a pwm callback is used to set/clear the configured pin.
+ */
+#include "audio.h"
+#include "ch.h"
+#include "hal.h"
+#if !defined(AUDIO_PIN)
+#    error "Audio feature enabled, but no pin selected - see docs/feature_audio under the ARM PWM settings"
+#endif
+extern bool    playing_note;
+extern bool    playing_melody;
+extern uint8_t note_timbre;
+static void pwm_audio_period_callback(PWMDriver *pwmp);
+static void pwm_audio_channel_interrupt_callback(PWMDriver *pwmp);
+static PWMConfig pwmCFG = {
+    .frequency = 100000, /* PWM clock frequency  */
+    // CHIBIOS-BUG? can't set the initial period to <2, or the pwm (hard or software) takes ~130ms with .frequency=500000 for a pwmChangePeriod to take effect; with no output=silence in the meantime
+    .period   = 2, /* initial PWM period (in ticks) 1S (1/10kHz=0.1mS 0.1ms*10000 ticks=1S) */
+    .callback = pwm_audio_period_callback,
+    .channels =
+        {
+            // software-PWM just needs another callback on any channel
+            {PWM_OUTPUT_ACTIVE_HIGH, pwm_audio_channel_interrupt_callback}, /* channel 0 -> TIMx_CH1 */
+            {PWM_OUTPUT_DISABLED, NULL},                                    /* channel 1 -> TIMx_CH2 */
+            {PWM_OUTPUT_DISABLED, NULL},                                    /* channel 2 -> TIMx_CH3 */
+            {PWM_OUTPUT_DISABLED, NULL}                                     /* channel 3 -> TIMx_CH4 */
+        },
+};
+static float channel_1_frequency = 0.0f;
+void         channel_1_set_frequency(float freq) {
+    channel_1_frequency = freq;
+    if (freq <= 0.0)  // a pause/rest has freq=0
+        return;
+    pwmcnt_t period = (pwmCFG.frequency / freq);
+    pwmChangePeriod(&AUDIO_PWM_DRIVER, period);
+    pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
+                     // adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
+                     PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
+}
+float channel_1_get_frequency(void) { return channel_1_frequency; }
+void channel_1_start(void) {
+    pwmStop(&AUDIO_PWM_DRIVER);
+    pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
+    pwmEnablePeriodicNotification(&AUDIO_PWM_DRIVER);
+    pwmEnableChannelNotification(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1);
+}
+void channel_1_stop(void) {
+    pwmStop(&AUDIO_PWM_DRIVER);
+    palClearLine(AUDIO_PIN);  // leave the line low, after last note was played
+#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+    palClearLine(AUDIO_PIN_ALT);  // leave the line low, after last note was played
+#endif
+}
+// generate a PWM signal on any pin, not necessarily the one connected to the timer
+static void pwm_audio_period_callback(PWMDriver *pwmp) {
+    (void)pwmp;
+    palClearLine(AUDIO_PIN);
+#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+    palSetLine(AUDIO_PIN_ALT);
+#endif
+}
+static void pwm_audio_channel_interrupt_callback(PWMDriver *pwmp) {
+    (void)pwmp;
+    if (channel_1_frequency > 0) {
+        palSetLine(AUDIO_PIN);  // generate a PWM signal on any pin, not necessarily the one connected to the timer
+#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+        palClearLine(AUDIO_PIN_ALT);
+#endif
+    }
+}
+static void gpt_callback(GPTDriver *gptp);
+GPTConfig   gptCFG = {
+    /* a whole note is one beat, which is - per definition in musical_notes.h - set to 64
+       the longest note is BREAVE_DOT=128+64=192, the shortest SIXTEENTH=4
+       the tempo (which might vary!) is in bpm (beats per minute)
+       therefore: if the timer ticks away at .frequency = (60*64)Hz,
+       and the .interval counts from 64 downwards - audio_update_state is
+       called just often enough to not miss anything
+    */
+    .frequency = 60 * 64,
+    .callback  = gpt_callback,
+};
+void audio_driver_initialize(void) {
+    pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
+    palSetLineMode(AUDIO_PIN, PAL_MODE_OUTPUT_PUSHPULL);
+    palClearLine(AUDIO_PIN);
+#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
+    palSetLineMode(AUDIO_PIN_ALT, PAL_MODE_OUTPUT_PUSHPULL);
+    palClearLine(AUDIO_PIN_ALT);
+#endif
+    pwmEnablePeriodicNotification(&AUDIO_PWM_DRIVER);  // enable pwm callbacks
+    pwmEnableChannelNotification(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1);
+    gptStart(&AUDIO_STATE_TIMER, &gptCFG);
+}
+void audio_driver_start(void) {
+    channel_1_stop();
+    channel_1_start();
+    if (playing_note || playing_melody) {
+        gptStartContinuous(&AUDIO_STATE_TIMER, 64);
+    }
+}
+void audio_driver_stop(void) {
+    channel_1_stop();
+    gptStopTimer(&AUDIO_STATE_TIMER);
+}
+/* a regular timer task, that checks the note to be currently played
+ * and updates the pwm to output that frequency
+ */
+static void gpt_callback(GPTDriver *gptp) {
+    float freq;  // TODO: freq_alt
+    if (audio_update_state()) {
+        freq = audio_get_processed_frequency(0);  // freq_alt would be index=1
+        channel_1_set_frequency(freq);
+    }
+}
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index fc4bb2ab3..63e85ae87 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -63,16 +63,16 @@ __attribute__((weak)) void i2c_init(void) {
        is_initialised = true;
        // Try releasing special pins for a short time
-        palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
+        palSetLineMode(I2C1_SCL_PIN, PAL_MODE_INPUT);
-        palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
+        palSetLineMode(I2C1_SDA_PIN, PAL_MODE_INPUT);
        chThdSleepMilliseconds(10);
 #if defined(USE_GPIOV1)
-        palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, I2C1_SCL_PAL_MODE);
+        palSetLineMode(I2C1_SCL_PIN, I2C1_SCL_PAL_MODE);
-        palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, I2C1_SDA_PAL_MODE);
+        palSetLineMode(I2C1_SDA_PIN, I2C1_SDA_PAL_MODE);
 #else
-        palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+        palSetLineMode(I2C1_SCL_PIN, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
-        palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+        palSetLineMode(I2C1_SDA_PIN, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
 #endif
    }
 }
@@ -102,7 +102,7 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
    i2cStart(&I2C_DRIVER, &i2cconfig);
    uint8_t complete_packet[length + 1];
-    for (uint8_t i = 0; i < length; i++) {
+    for (uint16_t i = 0; i < length; i++) {
        complete_packet[i + 1] = data[i];
    }
    complete_packet[0] = regaddr;
@@ -111,6 +111,21 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
    return chibios_to_qmk(&status);
 }
+i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
+    i2c_address = devaddr;
+    i2cStart(&I2C_DRIVER, &i2cconfig);
+    uint8_t complete_packet[length + 2];
+    for (uint16_t i = 0; i < length; i++) {
+        complete_packet[i + 2] = data[i];
+    }
+    complete_packet[0] = regaddr >> 8;
+    complete_packet[1] = regaddr & 0xFF;
+    msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 2, 0, 0, TIME_MS2I(timeout));
+    return chibios_to_qmk(&status);
+}
 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
    i2c_address = devaddr;
    i2cStart(&I2C_DRIVER, &i2cconfig);
@@ -118,4 +133,12 @@ i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16
    return chibios_to_qmk(&status);
 }
+i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
+    i2c_address = devaddr;
+    i2cStart(&I2C_DRIVER, &i2cconfig);
+    uint8_t register_packet[2] = {regaddr >> 8, regaddr & 0xFF};
+    msg_t   status             = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), register_packet, 2, data, length, TIME_MS2I(timeout));
+    return chibios_to_qmk(&status);
+}
 void i2c_stop(void) { i2cStop(&I2C_DRIVER); }
diff --git a/platforms/chibios/drivers/i2c_master.h b/platforms/chibios/drivers/i2c_master.h
index c68109acb..5f082e9d1 100644
--- a/platforms/chibios/drivers/i2c_master.h
+++ b/platforms/chibios/drivers/i2c_master.h
@@ -27,24 +27,11 @@
 #include <ch.h>
 #include <hal.h>
-#ifdef I2C1_BANK
+#ifndef I2C1_SCL_PIN
-#    define I2C1_SCL_BANK I2C1_BANK
+#    define I2C1_SCL_PIN B6
-#    define I2C1_SDA_BANK I2C1_BANK
 #endif
+#ifndef I2C1_SDA_PIN
-#ifndef I2C1_SCL_BANK
+#    define I2C1_SDA_PIN B7
-#    define I2C1_SCL_BANK GPIOB
-#endif
-#ifndef I2C1_SDA_BANK
-#    define I2C1_SDA_BANK GPIOB
-#endif
-#ifndef I2C1_SCL
-#    define I2C1_SCL 6
-#endif
-#ifndef I2C1_SDA
-#    define I2C1_SDA 7
 #endif
 #ifdef USE_I2CV1
@@ -83,10 +70,10 @@
 #ifdef USE_GPIOV1
 #    ifndef I2C1_SCL_PAL_MODE
-#        define I2C1_SCL_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#        define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
 #    endif
 #    ifndef I2C1_SDA_PAL_MODE
-#        define I2C1_SDA_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#        define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
 #    endif
 #else
 // The default PAL alternate modes are used to signal that the pins are used for I2C
@@ -109,5 +96,7 @@ i2c_status_t i2c_start(uint8_t address);
 i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
 void         i2c_stop(void);
diff --git a/platforms/chibios/drivers/ps2/ps2_io.c b/platforms/chibios/drivers/ps2/ps2_io.c
new file mode 100644
index 000000000..906d85d84
--- /dev/null
+++ b/platforms/chibios/drivers/ps2/ps2_io.c
@@ -0,0 +1,55 @@
+#include <stdbool.h>
+#include "ps2_io.h"
+// chibiOS headers
+#include "ch.h"
+#include "hal.h"
+/* Check port settings for clock and data line */
+#if !(defined(PS2_CLOCK_PIN))
+#    error "PS/2 clock setting is required in config.h"
+#endif
+#if !(defined(PS2_DATA_PIN))
+#    error "PS/2 data setting is required in config.h"
+#endif
+/*
+ * Clock
+ */
+void clock_init(void) {}
+void clock_lo(void) {
+    palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
+    palWriteLine(PS2_CLOCK_PIN, PAL_LOW);
+}
+void clock_hi(void) {
+    palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
+    palWriteLine(PS2_CLOCK_PIN, PAL_HIGH);
+}
+bool clock_in(void) {
+    palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_INPUT);
+    return palReadLine(PS2_CLOCK_PIN);
+}
+/*
+ * Data
+ */
+void data_init(void) {}
+void data_lo(void) {
+    palSetLineMode(PS2_DATA_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
+    palWriteLine(PS2_DATA_PIN, PAL_LOW);
+}
+void data_hi(void) {
+    palSetLineMode(PS2_DATA_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
+    palWriteLine(PS2_DATA_PIN, PAL_HIGH);
+}
+bool data_in(void) {
+    palSetLineMode(PS2_DATA_PIN, PAL_MODE_INPUT);
+    return palReadLine(PS2_DATA_PIN);
+}
diff --git a/platforms/chibios/drivers/serial.c b/platforms/chibios/drivers/serial.c
index f54fbcee4..ef6f0aa8d 100644
--- a/platforms/chibios/drivers/serial.c
+++ b/platforms/chibios/drivers/serial.c
@@ -19,7 +19,7 @@
 #    error "chSysPolledDelayX method not supported on this platform"
 #else
 #    undef wait_us
-#    define wait_us(x) chSysPolledDelayX(US2RTC(STM32_SYSCLK, x))
+#    define wait_us(x) chSysPolledDelayX(US2RTC(CPU_CLOCK, x))
 #endif
 #ifndef SELECT_SOFT_SERIAL_SPEED
diff --git a/platforms/chibios/drivers/serial_usart.c b/platforms/chibios/drivers/serial_usart.c
index ea4473791..124e4be68 100644
--- a/platforms/chibios/drivers/serial_usart.c
+++ b/platforms/chibios/drivers/serial_usart.c
@@ -104,9 +104,9 @@ static inline bool receive(uint8_t* destination, const size_t size) {
 __attribute__((weak)) void usart_init(void) {
 #    if defined(MCU_STM32)
 #        if defined(USE_GPIOV1)
-    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
 #        else
-    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
 #        endif
 #        if defined(USART_REMAP)
@@ -125,11 +125,11 @@ __attribute__((weak)) void usart_init(void) {
 __attribute__((weak)) void usart_init(void) {
 #    if defined(MCU_STM32)
 #        if defined(USE_GPIOV1)
-    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
    palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_INPUT);
 #        else
-    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
+    palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
-    palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_RX_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
+    palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_RX_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
 #        endif
 #        if defined(USART_REMAP)
diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c
index 28ddcbb2b..c592369dd 100644
--- a/platforms/chibios/drivers/spi_master.c
+++ b/platforms/chibios/drivers/spi_master.c
@@ -42,9 +42,9 @@ __attribute__((weak)) void spi_init(void) {
        palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), SPI_MOSI_PAL_MODE);
        palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), SPI_MISO_PAL_MODE);
 #else
-        palSetPadMode(PAL_PORT(SPI_SCK_PIN), PAL_PAD(SPI_SCK_PIN), PAL_MODE_ALTERNATE(SPI_SCK_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
+        palSetPadMode(PAL_PORT(SPI_SCK_PIN), PAL_PAD(SPI_SCK_PIN), PAL_MODE_ALTERNATE(SPI_SCK_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
-        palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), PAL_MODE_ALTERNATE(SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
+        palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), PAL_MODE_ALTERNATE(SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
-        palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), PAL_MODE_ALTERNATE(SPI_MISO_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
+        palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), PAL_MODE_ALTERNATE(SPI_MISO_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
 #endif
    }
 }
@@ -110,6 +110,31 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
            spiConfig.tar0 |= SPIx_CTARn_BR(8);
            break;
    }
+#elif defined(HT32)
+    spiConfig.cr0 = SPI_CR0_SELOEN;
+    spiConfig.cr1 = SPI_CR1_MODE | 8;  // 8 bits and in master mode
+    if (lsbFirst) {
+        spiConfig.cr1 |= SPI_CR1_FIRSTBIT;
+    }
+    switch (mode) {
+        case 0:
+            spiConfig.cr1 |= SPI_CR1_FORMAT_MODE0;
+            break;
+        case 1:
+            spiConfig.cr1 |= SPI_CR1_FORMAT_MODE1;
+            break;
+        case 2:
+            spiConfig.cr1 |= SPI_CR1_FORMAT_MODE2;
+            break;
+        case 3:
+            spiConfig.cr1 |= SPI_CR1_FORMAT_MODE3;
+            break;
+    }
+    spiConfig.cpr = (roundedDivisor - 1) >> 1;
 #else
    spiConfig.cr1 = 0;
diff --git a/platforms/chibios/drivers/spi_master.h b/platforms/chibios/drivers/spi_master.h
index b5a6ef143..6a3ce481f 100644
--- a/platforms/chibios/drivers/spi_master.h
+++ b/platforms/chibios/drivers/spi_master.h
@@ -33,7 +33,7 @@
 #ifndef SPI_SCK_PAL_MODE
 #    if defined(USE_GPIOV1)
-#        define SPI_SCK_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#        define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #    else
 #        define SPI_SCK_PAL_MODE 5
 #    endif
@@ -45,7 +45,7 @@
 #ifndef SPI_MOSI_PAL_MODE
 #    if defined(USE_GPIOV1)
-#        define SPI_MOSI_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#        define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #    else
 #        define SPI_MOSI_PAL_MODE 5
 #    endif
@@ -57,7 +57,7 @@
 #ifndef SPI_MISO_PAL_MODE
 #    if defined(USE_GPIOV1)
-#        define SPI_MISO_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#        define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #    else
 #        define SPI_MISO_PAL_MODE 5
 #    endif
diff --git a/platforms/chibios/drivers/uart.c b/platforms/chibios/drivers/uart.c
index 030335b34..0e8e0515a 100644
--- a/platforms/chibios/drivers/uart.c
+++ b/platforms/chibios/drivers/uart.c
@@ -29,11 +29,11 @@ void uart_init(uint32_t baud) {
        serialConfig.speed = baud;
 #if defined(USE_GPIOV1)
-        palSetLineMode(SD1_TX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+        palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
-        palSetLineMode(SD1_RX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+        palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
 #else
-        palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE(SD1_TX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+        palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE(SD1_TX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
-        palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE(SD1_RX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+        palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE(SD1_RX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
 #endif
        sdStart(&SERIAL_DRIVER, &serialConfig);
    }
diff --git a/platforms/chibios/drivers/ws2812.c b/platforms/chibios/drivers/ws2812.c
index 0d12e2fb7..b46c46ae5 100644
--- a/platforms/chibios/drivers/ws2812.c
+++ b/platforms/chibios/drivers/ws2812.c
@@ -6,7 +6,7 @@
 /* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */
 #ifndef NOP_FUDGE
-#    if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
+#    if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
 #        define NOP_FUDGE 0.4
 #    else
 #        error("NOP_FUDGE configuration required")
@@ -23,7 +23,7 @@
 #endif
 #define NUMBER_NOPS 6
-#define CYCLES_PER_SEC (STM32_SYSCLK / NUMBER_NOPS * NOP_FUDGE)
+#define CYCLES_PER_SEC (CPU_CLOCK / NUMBER_NOPS * NOP_FUDGE)
 #define NS_PER_SEC (1000000000L)  // Note that this has to be SIGNED since we want to be able to check for negative values of derivatives
 #define NS_PER_CYCLE (NS_PER_SEC / CYCLES_PER_SEC)
 #define NS_TO_CYCLES(n) ((n) / NS_PER_CYCLE)
diff --git a/platforms/chibios/drivers/ws2812_pwm.c b/platforms/chibios/drivers/ws2812_pwm.c
index e6af55b6b..c17b9cd4e 100644
--- a/platforms/chibios/drivers/ws2812_pwm.c
+++ b/platforms/chibios/drivers/ws2812_pwm.c
@@ -5,7 +5,9 @@
 /* Adapted from https://github.com/joewa/WS2812-LED-Driver_ChibiOS/ */
 #ifdef RGBW
-#    error "RGBW not supported"
+#    define WS2812_CHANNELS 4
+#else
+#    define WS2812_CHANNELS 3
 #endif
 #ifndef WS2812_PWM_DRIVER
@@ -40,15 +42,15 @@
 // Default Push Pull
 #ifndef WS2812_EXTERNAL_PULLUP
 #    if defined(USE_GPIOV1)
-#        define WS2812_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #    else
-#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING
+#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST | PAL_PUPDR_FLOATING
 #    endif
 #else
 #    if defined(USE_GPIOV1)
-#        define WS2812_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE_OPENDRAIN
 #    else
-#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING
+#        define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN | PAL_OUTPUT_SPEED_HIGHEST | PAL_PUPDR_FLOATING
 #    endif
 #endif
@@ -59,7 +61,7 @@
 /* --- PRIVATE CONSTANTS ---------------------------------------------------- */
-#define WS2812_PWM_FREQUENCY (STM32_SYSCLK / 2)                             /**< Clock frequency of PWM, must be valid with respect to system clock! */
+#define WS2812_PWM_FREQUENCY (CPU_CLOCK / 2)                                /**< Clock frequency of PWM, must be valid with respect to system clock! */
 #define WS2812_PWM_PERIOD (WS2812_PWM_FREQUENCY / WS2812_PWM_TARGET_PERIOD) /**< Clock period in ticks. 1 / 800kHz = 1.25 uS (as per datasheet) */
 /**
@@ -68,8 +70,9 @@
 * The reset period for each frame is defined in WS2812_TRST_US.
 * Calculate the number of zeroes to add at the end assuming 1.25 uS/bit:
 */
+#define WS2812_COLOR_BITS (WS2812_CHANNELS * 8)
 #define WS2812_RESET_BIT_N (1000 * WS2812_TRST_US / 1250)
-#define WS2812_COLOR_BIT_N (RGBLED_NUM * 24)                   /**< Number of data bits */
+#define WS2812_COLOR_BIT_N (RGBLED_NUM * WS2812_COLOR_BITS)    /**< Number of data bits */
 #define WS2812_BIT_N (WS2812_COLOR_BIT_N + WS2812_RESET_BIT_N) /**< Total number of bits in a frame */
 /**
@@ -114,7 +117,7 @@
 *
 * @return                          The bit index
 */
-#define WS2812_BIT(led, byte, bit) (24 * (led) + 8 * (byte) + (7 - (bit)))
+#define WS2812_BIT(led, byte, bit) (WS2812_COLOR_BITS * (led) + 8 * (byte) + (7 - (bit)))
 #if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
 /**
@@ -228,6 +231,20 @@
 #    define WS2812_BLUE_BIT(led, bit) WS2812_BIT((led), 0, (bit))
 #endif
+#ifdef RGBW
+/**
+ * @brief   Determine the index in @ref ws2812_frame_buffer "the frame buffer" of a given white bit
+ *
+ * @note    The white byte is the last byte in the color packet
+ *
+ * @param[in] led:                  The led index [0, @ref WS2812_LED_N)
+ * @param[in] bit:                  The bit index [0, 7]
+ *
+ * @return                          The bit index
+ */
+#    define WS2812_WHITE_BIT(led, bit) WS2812_BIT((led), 3, (bit))
+#endif
 /* --- PRIVATE VARIABLES ---------------------------------------------------- */
 static uint32_t ws2812_frame_buffer[WS2812_BIT_N + 1]; /**< Buffer for a frame */
@@ -296,6 +313,17 @@ void ws2812_write_led(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b) {
        ws2812_frame_buffer[WS2812_BLUE_BIT(led_number, bit)]  = ((b >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
    }
 }
+void ws2812_write_led_rgbw(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b, uint8_t w) {
+    // Write color to frame buffer
+    for (uint8_t bit = 0; bit < 8; bit++) {
+        ws2812_frame_buffer[WS2812_RED_BIT(led_number, bit)]   = ((r >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
+        ws2812_frame_buffer[WS2812_GREEN_BIT(led_number, bit)] = ((g >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
+        ws2812_frame_buffer[WS2812_BLUE_BIT(led_number, bit)]  = ((b >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
+#ifdef RGBW
+        ws2812_frame_buffer[WS2812_WHITE_BIT(led_number, bit)] = ((w >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
+#endif
+    }
+}
 // Setleds for standard RGB
 void ws2812_setleds(LED_TYPE* ledarray, uint16_t leds) {
@@ -306,6 +334,10 @@ void ws2812_setleds(LED_TYPE* ledarray, uint16_t leds) {
    }
    for (uint16_t i = 0; i < leds; i++) {
+#ifdef RGBW
+        ws2812_write_led_rgbw(i, ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
+#else
        ws2812_write_led(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
+#endif
    }
 }
diff --git a/platforms/chibios/drivers/ws2812_spi.c b/platforms/chibios/drivers/ws2812_spi.c
index fe14b478a..62722f466 100644
--- a/platforms/chibios/drivers/ws2812_spi.c
+++ b/platforms/chibios/drivers/ws2812_spi.c
@@ -3,10 +3,6 @@
 /* Adapted from https://github.com/gamazeps/ws2812b-chibios-SPIDMA/ */
-#ifdef RGBW
-#    error "RGBW not supported"
-#endif
 // Define the spi your LEDs are plugged to here
 #ifndef WS2812_SPI
 #    define WS2812_SPI SPID1
@@ -24,15 +20,15 @@
 // Default Push Pull
 #ifndef WS2812_EXTERNAL_PULLUP
 #    if defined(USE_GPIOV1)
-#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #    else
-#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL
+#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL
 #    endif
 #else
 #    if defined(USE_GPIOV1)
-#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE_OPENDRAIN
 #    else
-#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN
+#        define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN
 #    endif
 #endif
@@ -68,14 +64,18 @@
 #endif
 #if defined(USE_GPIOV1)
-#    define WS2812_SCK_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
+#    define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
 #else
-#    define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_SCK_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL
+#    define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_SCK_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL
 #endif
 #define BYTES_FOR_LED_BYTE 4
-#define NB_COLORS 3
+#ifdef RGBW
-#define BYTES_FOR_LED (BYTES_FOR_LED_BYTE * NB_COLORS)
+#    define WS2812_CHANNELS 4
+#else
+#    define WS2812_CHANNELS 3
+#endif
+#define BYTES_FOR_LED (BYTES_FOR_LED_BYTE * WS2812_CHANNELS)
 #define DATA_SIZE (BYTES_FOR_LED * RGBLED_NUM)
 #define RESET_SIZE (1000 * WS2812_TRST_US / (2 * 1250))
 #define PREAMBLE_SIZE 4
@@ -116,6 +116,9 @@ static void set_led_color_rgb(LED_TYPE color, int pos) {
    for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE + j] = get_protocol_eq(color.g, j);
    for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE * 2 + j] = get_protocol_eq(color.r, j);
 #endif
+#ifdef RGBW
+    for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE * 4 + j] = get_protocol_eq(color.w, j);
+#endif
 }
 void ws2812_init(void) {
diff --git a/platforms/chibios/flash.mk b/platforms/chibios/flash.mk
index c0b32c2f2..31f69595d 100644
--- a/platforms/chibios/flash.mk
+++ b/platforms/chibios/flash.mk
@@ -82,6 +82,8 @@ else ifeq ($(strip $(MCU_FAMILY)),MIMXRT1062)
        $(UNSYNC_OUTPUT_CMD) && $(call EXEC_TEENSY)
 else ifeq ($(strip $(MCU_FAMILY)),STM32)
        $(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
+else ifeq ($(strip $(MCU_FAMILY)),GD32V)
+        $(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
 else
        $(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_BOOTLOADER)"
 endif