diff options
Diffstat (limited to 'tmk_core')
| -rw-r--r-- | tmk_core/common/arm_atsam/timer.c | 20 | ||||
| -rw-r--r-- | tmk_core/common/wait.h | 4 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/arm_atsam_protocol.h | 2 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/clks.c | 90 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/clks.h | 5 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/i2c_master.c | 4 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/led_matrix.c | 4 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/main_arm_atsam.c | 18 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/usb/udi_cdc.c | 8 | ||||
| -rw-r--r-- | tmk_core/protocol/arm_atsam/usb/usb2422.c | 15 |
10 files changed, 55 insertions, 115 deletions
diff --git a/tmk_core/common/arm_atsam/timer.c b/tmk_core/common/arm_atsam/timer.c index bcfe5002c..6c3905e30 100644 --- a/tmk_core/common/arm_atsam/timer.c +++ b/tmk_core/common/arm_atsam/timer.c | |||
| @@ -9,7 +9,7 @@ void set_time(uint64_t tset) | |||
| 9 | 9 | ||
| 10 | void timer_init(void) | 10 | void timer_init(void) |
| 11 | { | 11 | { |
| 12 | ms_clk = 0; | 12 | timer_clear(); |
| 13 | } | 13 | } |
| 14 | 14 | ||
| 15 | uint16_t timer_read(void) | 15 | uint16_t timer_read(void) |
| @@ -37,23 +37,7 @@ uint32_t timer_elapsed32(uint32_t tlast) | |||
| 37 | return TIMER_DIFF_32(timer_read32(), tlast); | 37 | return TIMER_DIFF_32(timer_read32(), tlast); |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | uint32_t timer_elapsed64(uint32_t tlast) | ||
| 41 | { | ||
| 42 | uint64_t tnow = timer_read64(); | ||
| 43 | return (tnow >= tlast ? tnow - tlast : UINT64_MAX - tlast + tnow); | ||
| 44 | } | ||
| 45 | |||
| 46 | void timer_clear(void) | 40 | void timer_clear(void) |
| 47 | { | 41 | { |
| 48 | ms_clk = 0; | 42 | set_time(0); |
| 49 | } | ||
| 50 | |||
| 51 | void wait_ms(uint64_t msec) | ||
| 52 | { | ||
| 53 | CLK_delay_ms(msec); | ||
| 54 | } | ||
| 55 | |||
| 56 | void wait_us(uint16_t usec) | ||
| 57 | { | ||
| 58 | CLK_delay_us(usec); | ||
| 59 | } | 43 | } |
diff --git a/tmk_core/common/wait.h b/tmk_core/common/wait.h index a7cded942..a77840bce 100644 --- a/tmk_core/common/wait.h +++ b/tmk_core/common/wait.h | |||
| @@ -15,6 +15,10 @@ extern "C" { | |||
| 15 | # include "ch.h" | 15 | # include "ch.h" |
| 16 | # define wait_ms(ms) chThdSleepMilliseconds(ms) | 16 | # define wait_ms(ms) chThdSleepMilliseconds(ms) |
| 17 | # define wait_us(us) chThdSleepMicroseconds(us) | 17 | # define wait_us(us) chThdSleepMicroseconds(us) |
| 18 | #elif defined PROTOCOL_ARM_ATSAM | ||
| 19 | # include "clks.h" | ||
| 20 | # define wait_ms(ms) CLK_delay_ms(ms) | ||
| 21 | # define wait_us(us) CLK_delay_us(us) | ||
| 18 | #elif defined(__arm__) | 22 | #elif defined(__arm__) |
| 19 | # include "wait_api.h" | 23 | # include "wait_api.h" |
| 20 | #else // Unit tests | 24 | #else // Unit tests |
diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h index 2ba099174..928af8c7e 100644 --- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h +++ b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h | |||
| @@ -21,8 +21,10 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
| 21 | #include "samd51j18a.h" | 21 | #include "samd51j18a.h" |
| 22 | #include "md_bootloader.h" | 22 | #include "md_bootloader.h" |
| 23 | 23 | ||
| 24 | #include "timer.h" | ||
| 24 | #include "d51_util.h" | 25 | #include "d51_util.h" |
| 25 | #include "clks.h" | 26 | #include "clks.h" |
| 27 | #include "wait.h" | ||
| 26 | #include "adc.h" | 28 | #include "adc.h" |
| 27 | #include "i2c_master.h" | 29 | #include "i2c_master.h" |
| 28 | #include "spi.h" | 30 | #include "spi.h" |
diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c index 8768d0a99..1ff318e59 100644 --- a/tmk_core/protocol/arm_atsam/clks.c +++ b/tmk_core/protocol/arm_atsam/clks.c | |||
| @@ -21,8 +21,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
| 21 | 21 | ||
| 22 | volatile clk_t system_clks; | 22 | volatile clk_t system_clks; |
| 23 | volatile uint64_t ms_clk; | 23 | volatile uint64_t ms_clk; |
| 24 | 24 | uint32_t usec_delay_mult; | |
| 25 | volatile uint8_t us_delay_done; | 25 | #define USEC_DELAY_LOOP_CYCLES 3 //Sum of instruction cycles in us delay loop |
| 26 | 26 | ||
| 27 | const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5}; | 27 | const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5}; |
| 28 | const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; | 28 | const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; |
| @@ -73,6 +73,9 @@ void CLK_oscctrl_init(void) | |||
| 73 | 73 | ||
| 74 | system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; | 74 | system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; |
| 75 | 75 | ||
| 76 | usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000); | ||
| 77 | if (usec_delay_mult < 1) usec_delay_mult = 1; //Never allow a multiplier of zero | ||
| 78 | |||
| 76 | DBGC(DC_CLK_OSC_INIT_COMPLETE); | 79 | DBGC(DC_CLK_OSC_INIT_COMPLETE); |
| 77 | } | 80 | } |
| 78 | 81 | ||
| @@ -158,23 +161,11 @@ void TC4_Handler() | |||
| 158 | } | 161 | } |
| 159 | } | 162 | } |
| 160 | 163 | ||
| 161 | void TC5_Handler() | ||
| 162 | { | ||
| 163 | if (TC5->COUNT16.INTFLAG.bit.MC0) | ||
| 164 | { | ||
| 165 | TC5->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0; | ||
| 166 | us_delay_done = 1; | ||
| 167 | TC5->COUNT16.CTRLA.bit.ENABLE = 0; | ||
| 168 | while (TC5->COUNT16.SYNCBUSY.bit.ENABLE) {} | ||
| 169 | } | ||
| 170 | } | ||
| 171 | |||
| 172 | uint32_t CLK_enable_timebase(void) | 164 | uint32_t CLK_enable_timebase(void) |
| 173 | { | 165 | { |
| 174 | Gclk *pgclk = GCLK; | 166 | Gclk *pgclk = GCLK; |
| 175 | Mclk *pmclk = MCLK; | 167 | Mclk *pmclk = MCLK; |
| 176 | Tc *ptc4 = TC4; | 168 | Tc *ptc4 = TC4; |
| 177 | Tc *ptc5 = TC5; | ||
| 178 | Tc *ptc0 = TC0; | 169 | Tc *ptc0 = TC0; |
| 179 | Evsys *pevsys = EVSYS; | 170 | Evsys *pevsys = EVSYS; |
| 180 | 171 | ||
| @@ -189,11 +180,6 @@ uint32_t CLK_enable_timebase(void) | |||
| 189 | pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; | 180 | pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; |
| 190 | pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1; | 181 | pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1; |
| 191 | 182 | ||
| 192 | //unmask TC5 sourcegclk2 to TC5 | ||
| 193 | pmclk->APBCMASK.bit.TC5_ = 1; | ||
| 194 | pgclk->PCHCTRL[TC5_GCLK_ID].bit.GEN = GEN_TC45; | ||
| 195 | pgclk->PCHCTRL[TC5_GCLK_ID].bit.CHEN = 1; | ||
| 196 | |||
| 197 | //configure TC4 | 183 | //configure TC4 |
| 198 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN); | 184 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN); |
| 199 | ptc4->COUNT16.CTRLA.bit.ENABLE = 0; | 185 | ptc4->COUNT16.CTRLA.bit.ENABLE = 0; |
| @@ -220,30 +206,6 @@ uint32_t CLK_enable_timebase(void) | |||
| 220 | 206 | ||
| 221 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE); | 207 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE); |
| 222 | 208 | ||
| 223 | //configure TC5 | ||
| 224 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_BEGIN); | ||
| 225 | ptc5->COUNT16.CTRLA.bit.ENABLE = 0; | ||
| 226 | while (ptc5->COUNT16.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_DISABLE); } | ||
| 227 | ptc5->COUNT16.CTRLA.bit.SWRST = 1; | ||
| 228 | while (ptc5->COUNT16.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_1); } | ||
| 229 | while (ptc5->COUNT16.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_2); } | ||
| 230 | |||
| 231 | //CTRLA defaults | ||
| 232 | //CTRLB as default, counting up | ||
| 233 | ptc5->COUNT16.CTRLBCLR.reg = 5; | ||
| 234 | while (ptc5->COUNT16.SYNCBUSY.bit.CTRLB) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_CLTRB); } | ||
| 235 | //ptc5->COUNT16.DBGCTRL.bit.DBGRUN = 1; | ||
| 236 | |||
| 237 | //wave mode | ||
| 238 | ptc5->COUNT16.WAVE.bit.WAVEGEN = 1; //MFRQ match frequency mode, toggle each CC match | ||
| 239 | //generate event for next stage | ||
| 240 | ptc5->COUNT16.EVCTRL.bit.MCEO0 = 1; | ||
| 241 | |||
| 242 | NVIC_EnableIRQ(TC5_IRQn); | ||
| 243 | ptc5->COUNT16.INTENSET.bit.MC0 = 1; | ||
| 244 | |||
| 245 | DBGC(DC_CLK_ENABLE_TIMEBASE_TC5_COMPLETE); | ||
| 246 | |||
| 247 | //unmask TC0,1, sourcegclk2 to TC0,1 | 209 | //unmask TC0,1, sourcegclk2 to TC0,1 |
| 248 | pmclk->APBAMASK.bit.TC0_ = 1; | 210 | pmclk->APBAMASK.bit.TC0_ = 1; |
| 249 | pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; | 211 | pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; |
| @@ -289,37 +251,27 @@ uint32_t CLK_enable_timebase(void) | |||
| 289 | return 0; | 251 | return 0; |
| 290 | } | 252 | } |
| 291 | 253 | ||
| 292 | uint32_t CLK_get_ms(void) | 254 | void CLK_delay_us(uint32_t usec) |
| 293 | { | 255 | { |
| 294 | return ms_clk; | 256 | asm ( |
| 295 | } | 257 | "CBZ R0, return\n\t" //If usec == 0, branch to return label |
| 296 | 258 | ); | |
| 297 | void CLK_delay_us(uint16_t usec) | 259 | asm ( |
| 298 | { | 260 | "MULS R0, %0\n\t" //Multiply R0(usec) by usec_delay_mult and store in R0 |
| 299 | us_delay_done = 0; | 261 | ".balign 16\n\t" //Ensure loop is aligned for fastest performance |
| 300 | 262 | "loop: SUBS R0, #1\n\t" //Subtract 1 from R0 and update flags (1 cycle) | |
| 301 | if (TC5->COUNT16.CTRLA.bit.ENABLE) | 263 | "BNE loop\n\t" //Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles |
| 302 | { | 264 | "return:\n\t" //Return label |
| 303 | TC5->COUNT16.CTRLA.bit.ENABLE = 0; | 265 | : //No output registers |
| 304 | while (TC5->COUNT16.SYNCBUSY.bit.ENABLE) {} | 266 | : "r" (usec_delay_mult) //For %0 |
| 305 | } | 267 | ); |
| 306 | 268 | //Note: BX LR generated | |
| 307 | if (usec < 10) usec = 0; | ||
| 308 | else usec -= 10; | ||
| 309 | |||
| 310 | TC5->COUNT16.CC[0].reg = usec; | ||
| 311 | while (TC5->COUNT16.SYNCBUSY.bit.CC0) {} | ||
| 312 | |||
| 313 | TC5->COUNT16.CTRLA.bit.ENABLE = 1; | ||
| 314 | while (TC5->COUNT16.SYNCBUSY.bit.ENABLE) {} | ||
| 315 | |||
| 316 | while (!us_delay_done) {} | ||
| 317 | } | 269 | } |
| 318 | 270 | ||
| 319 | void CLK_delay_ms(uint64_t msec) | 271 | void CLK_delay_ms(uint64_t msec) |
| 320 | { | 272 | { |
| 321 | msec += CLK_get_ms(); | 273 | msec += timer_read64(); |
| 322 | while (msec > CLK_get_ms()) {} | 274 | while (msec > timer_read64()) {} |
| 323 | } | 275 | } |
| 324 | 276 | ||
| 325 | void clk_enable_sercom_apbmask(int sercomn) | 277 | void clk_enable_sercom_apbmask(int sercomn) |
diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h index 96819bfdd..1b01a1764 100644 --- a/tmk_core/protocol/arm_atsam/clks.h +++ b/tmk_core/protocol/arm_atsam/clks.h | |||
| @@ -77,9 +77,8 @@ void CLK_oscctrl_init(void); | |||
| 77 | void CLK_reset_time(void); | 77 | void CLK_reset_time(void); |
| 78 | uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq); | 78 | uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq); |
| 79 | uint32_t CLK_enable_timebase(void); | 79 | uint32_t CLK_enable_timebase(void); |
| 80 | uint32_t CLK_get_ms(void); | 80 | uint64_t timer_read64(void); |
| 81 | uint64_t CLK_get_us(void); | 81 | void CLK_delay_us(uint32_t usec); |
| 82 | void CLK_delay_us(uint16_t usec); | ||
| 83 | void CLK_delay_ms(uint64_t msec); | 82 | void CLK_delay_ms(uint64_t msec); |
| 84 | 83 | ||
| 85 | uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq); | 84 | uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq); |
diff --git a/tmk_core/protocol/arm_atsam/i2c_master.c b/tmk_core/protocol/arm_atsam/i2c_master.c index f608a79cc..d91a851f3 100644 --- a/tmk_core/protocol/arm_atsam/i2c_master.c +++ b/tmk_core/protocol/arm_atsam/i2c_master.c | |||
| @@ -265,12 +265,12 @@ uint8_t I2C3733_Init_Control(void) | |||
| 265 | //USB state machine will enable driver when communication is ready | 265 | //USB state machine will enable driver when communication is ready |
| 266 | I2C3733_Control_Set(0); | 266 | I2C3733_Control_Set(0); |
| 267 | 267 | ||
| 268 | CLK_delay_ms(1); | 268 | wait_ms(1); |
| 269 | 269 | ||
| 270 | sr_exp_data.bit.IRST = 0; | 270 | sr_exp_data.bit.IRST = 0; |
| 271 | SR_EXP_WriteData(); | 271 | SR_EXP_WriteData(); |
| 272 | 272 | ||
| 273 | CLK_delay_ms(1); | 273 | wait_ms(1); |
| 274 | 274 | ||
| 275 | DBGC(DC_I2C3733_INIT_CONTROL_COMPLETE); | 275 | DBGC(DC_I2C3733_INIT_CONTROL_COMPLETE); |
| 276 | 276 | ||
diff --git a/tmk_core/protocol/arm_atsam/led_matrix.c b/tmk_core/protocol/arm_atsam/led_matrix.c index e914fc80e..9ef7393a2 100644 --- a/tmk_core/protocol/arm_atsam/led_matrix.c +++ b/tmk_core/protocol/arm_atsam/led_matrix.c | |||
| @@ -494,11 +494,11 @@ void led_matrix_task(void) | |||
| 494 | if (led_enabled) | 494 | if (led_enabled) |
| 495 | { | 495 | { |
| 496 | //If an update may run and frame processing has completed | 496 | //If an update may run and frame processing has completed |
| 497 | if (CLK_get_ms() >= led_next_run && led_cur == lede) | 497 | if (timer_read64() >= led_next_run && led_cur == lede) |
| 498 | { | 498 | { |
| 499 | uint8_t drvid; | 499 | uint8_t drvid; |
| 500 | 500 | ||
| 501 | led_next_run = CLK_get_ms() + LED_UPDATE_RATE; //Set next frame update time | 501 | led_next_run = timer_read64() + LED_UPDATE_RATE; //Set next frame update time |
| 502 | 502 | ||
| 503 | //NOTE: GCR does not need to be timed with LED processing, but there is really no harm | 503 | //NOTE: GCR does not need to be timed with LED processing, but there is really no harm |
| 504 | if (gcr_actual != gcr_actual_last) | 504 | if (gcr_actual != gcr_actual_last) |
diff --git a/tmk_core/protocol/arm_atsam/main_arm_atsam.c b/tmk_core/protocol/arm_atsam/main_arm_atsam.c index 2bda7d7c7..eaad66e9f 100644 --- a/tmk_core/protocol/arm_atsam/main_arm_atsam.c +++ b/tmk_core/protocol/arm_atsam/main_arm_atsam.c | |||
| @@ -159,7 +159,7 @@ void send_consumer(uint16_t data) | |||
| 159 | 159 | ||
| 160 | void main_subtask_usb_state(void) | 160 | void main_subtask_usb_state(void) |
| 161 | { | 161 | { |
| 162 | static uint32_t fsmstate_on_delay = 0; //Delay timer to be sure USB is actually operating before bringing up hardware | 162 | static uint64_t fsmstate_on_delay = 0; //Delay timer to be sure USB is actually operating before bringing up hardware |
| 163 | uint8_t fsmstate_now = USB->DEVICE.FSMSTATUS.reg; //Current state from hardware register | 163 | uint8_t fsmstate_now = USB->DEVICE.FSMSTATUS.reg; //Current state from hardware register |
| 164 | 164 | ||
| 165 | if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) //If USB SUSPENDED | 165 | if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) //If USB SUSPENDED |
| @@ -188,9 +188,9 @@ void main_subtask_usb_state(void) | |||
| 188 | { | 188 | { |
| 189 | if (fsmstate_on_delay == 0) //If ON delay timer is cleared | 189 | if (fsmstate_on_delay == 0) //If ON delay timer is cleared |
| 190 | { | 190 | { |
| 191 | fsmstate_on_delay = CLK_get_ms() + 250; //Set ON delay timer | 191 | fsmstate_on_delay = timer_read64() + 250; //Set ON delay timer |
| 192 | } | 192 | } |
| 193 | else if (CLK_get_ms() > fsmstate_on_delay) //Else if ON delay timer is active and timed out | 193 | else if (timer_read64() > fsmstate_on_delay) //Else if ON delay timer is active and timed out |
| 194 | { | 194 | { |
| 195 | suspend_wakeup_init(); //Run wakeup routine | 195 | suspend_wakeup_init(); //Run wakeup routine |
| 196 | g_usb_state = fsmstate_now; //Save current USB state | 196 | g_usb_state = fsmstate_now; //Save current USB state |
| @@ -214,9 +214,9 @@ void main_subtask_power_check(void) | |||
| 214 | { | 214 | { |
| 215 | static uint64_t next_5v_checkup = 0; | 215 | static uint64_t next_5v_checkup = 0; |
| 216 | 216 | ||
| 217 | if (CLK_get_ms() > next_5v_checkup) | 217 | if (timer_read64() > next_5v_checkup) |
| 218 | { | 218 | { |
| 219 | next_5v_checkup = CLK_get_ms() + 5; | 219 | next_5v_checkup = timer_read64() + 5; |
| 220 | 220 | ||
| 221 | v_5v = adc_get(ADC_5V); | 221 | v_5v = adc_get(ADC_5V); |
| 222 | v_5v_avg = 0.9 * v_5v_avg + 0.1 * v_5v; | 222 | v_5v_avg = 0.9 * v_5v_avg + 0.1 * v_5v; |
| @@ -229,9 +229,9 @@ void main_subtask_usb_extra_device(void) | |||
| 229 | { | 229 | { |
| 230 | static uint64_t next_usb_checkup = 0; | 230 | static uint64_t next_usb_checkup = 0; |
| 231 | 231 | ||
| 232 | if (CLK_get_ms() > next_usb_checkup) | 232 | if (timer_read64() > next_usb_checkup) |
| 233 | { | 233 | { |
| 234 | next_usb_checkup = CLK_get_ms() + 10; | 234 | next_usb_checkup = timer_read64() + 10; |
| 235 | 235 | ||
| 236 | USB_HandleExtraDevice(); | 236 | USB_HandleExtraDevice(); |
| 237 | } | 237 | } |
| @@ -325,9 +325,9 @@ int main(void) | |||
| 325 | keyboard_task(); | 325 | keyboard_task(); |
| 326 | 326 | ||
| 327 | #ifdef CONSOLE_ENABLE | 327 | #ifdef CONSOLE_ENABLE |
| 328 | if (CLK_get_ms() > next_print) | 328 | if (timer_read64() > next_print) |
| 329 | { | 329 | { |
| 330 | next_print = CLK_get_ms() + 250; | 330 | next_print = timer_read64() + 250; |
| 331 | //Add any debug information here that you want to see very often | 331 | //Add any debug information here that you want to see very often |
| 332 | //dprintf("5v=%u 5vu=%u dlow=%u dhi=%u gca=%u gcd=%u\r\n", v_5v, v_5v_avg, v_5v_avg - V5_LOW, v_5v_avg - V5_HIGH, gcr_actual, gcr_desired); | 332 | //dprintf("5v=%u 5vu=%u dlow=%u dhi=%u gca=%u gcd=%u\r\n", v_5v, v_5v_avg, v_5v_avg - V5_LOW, v_5v_avg - V5_HIGH, gcr_actual, gcr_desired); |
| 333 | } | 333 | } |
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_cdc.c b/tmk_core/protocol/arm_atsam/usb/udi_cdc.c index 5f3c289e8..ffe3526db 100644 --- a/tmk_core/protocol/arm_atsam/usb/udi_cdc.c +++ b/tmk_core/protocol/arm_atsam/usb/udi_cdc.c | |||
| @@ -1227,9 +1227,9 @@ uint32_t cdc_tx_send_time_next; | |||
| 1227 | 1227 | ||
| 1228 | void CDC_send(void) | 1228 | void CDC_send(void) |
| 1229 | { | 1229 | { |
| 1230 | while (CLK_get_ms() < cdc_tx_send_time_next); | 1230 | while (timer_read64() < cdc_tx_send_time_next); |
| 1231 | udi_cdc_tx_send(0); | 1231 | udi_cdc_tx_send(0); |
| 1232 | cdc_tx_send_time_next = CLK_get_ms() + CDC_SEND_INTERVAL; | 1232 | cdc_tx_send_time_next = timer_read64() + CDC_SEND_INTERVAL; |
| 1233 | } | 1233 | } |
| 1234 | 1234 | ||
| 1235 | uint32_t CDC_print(char *printbuf) | 1235 | uint32_t CDC_print(char *printbuf) |
| @@ -1238,7 +1238,7 @@ uint32_t CDC_print(char *printbuf) | |||
| 1238 | char *buf = printbuf; | 1238 | char *buf = printbuf; |
| 1239 | char c; | 1239 | char c; |
| 1240 | 1240 | ||
| 1241 | if (CLK_get_ms() < 5000) return 0; | 1241 | if (timer_read64() < 5000) return 0; |
| 1242 | 1242 | ||
| 1243 | while ((c = *buf++) != 0 && !(count >= MAX_PRINT)) | 1243 | while ((c = *buf++) != 0 && !(count >= MAX_PRINT)) |
| 1244 | { | 1244 | { |
| @@ -1339,7 +1339,7 @@ void CDC_init(void) | |||
| 1339 | inbuf.count = 0; | 1339 | inbuf.count = 0; |
| 1340 | inbuf.lastcount = 0; | 1340 | inbuf.lastcount = 0; |
| 1341 | printbuf[0] = 0; | 1341 | printbuf[0] = 0; |
| 1342 | cdc_tx_send_time_next = CLK_get_ms() + CDC_SEND_INTERVAL; | 1342 | cdc_tx_send_time_next = timer_read64() + CDC_SEND_INTERVAL; |
| 1343 | } | 1343 | } |
| 1344 | 1344 | ||
| 1345 | #else //CDC line 62 | 1345 | #else //CDC line 62 |
diff --git a/tmk_core/protocol/arm_atsam/usb/usb2422.c b/tmk_core/protocol/arm_atsam/usb/usb2422.c index ac19bf4ea..d6e192242 100644 --- a/tmk_core/protocol/arm_atsam/usb/usb2422.c +++ b/tmk_core/protocol/arm_atsam/usb/usb2422.c | |||
| @@ -64,7 +64,7 @@ void USB_write2422_block(void) | |||
| 64 | i2c0_transmit(USB2422_ADDR, dest, 34, 50000); | 64 | i2c0_transmit(USB2422_ADDR, dest, 34, 50000); |
| 65 | SERCOM0->I2CM.CTRLB.bit.CMD = 0x03; | 65 | SERCOM0->I2CM.CTRLB.bit.CMD = 0x03; |
| 66 | while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) { DBGC(DC_USB_WRITE2422_BLOCK_SYNC_SYSOP); } | 66 | while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) { DBGC(DC_USB_WRITE2422_BLOCK_SYNC_SYSOP); } |
| 67 | CLK_delay_us(100); | 67 | wait_us(100); |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | DBGC(DC_USB_WRITE2422_BLOCK_COMPLETE); | 70 | DBGC(DC_USB_WRITE2422_BLOCK_COMPLETE); |
| @@ -135,7 +135,7 @@ void USB2422_init(void) | |||
| 135 | sr_exp_data.bit.HUB_RESET_N = 1; //reset high | 135 | sr_exp_data.bit.HUB_RESET_N = 1; //reset high |
| 136 | SR_EXP_WriteData(); | 136 | SR_EXP_WriteData(); |
| 137 | 137 | ||
| 138 | CLK_delay_us(100); | 138 | wait_us(100); |
| 139 | 139 | ||
| 140 | #ifndef MD_BOOTLOADER | 140 | #ifndef MD_BOOTLOADER |
| 141 | 141 | ||
| @@ -154,10 +154,9 @@ void USB_reset(void) | |||
| 154 | //pulse reset for at least 1 usec | 154 | //pulse reset for at least 1 usec |
| 155 | sr_exp_data.bit.HUB_RESET_N = 0; //reset low | 155 | sr_exp_data.bit.HUB_RESET_N = 0; //reset low |
| 156 | SR_EXP_WriteData(); | 156 | SR_EXP_WriteData(); |
| 157 | CLK_delay_us(1); | 157 | wait_us(2); |
| 158 | sr_exp_data.bit.HUB_RESET_N = 1; //reset high to run | 158 | sr_exp_data.bit.HUB_RESET_N = 1; //reset high to run |
| 159 | SR_EXP_WriteData(); | 159 | SR_EXP_WriteData(); |
| 160 | CLK_delay_us(1); | ||
| 161 | 160 | ||
| 162 | DBGC(DC_USB_RESET_COMPLETE); | 161 | DBGC(DC_USB_RESET_COMPLETE); |
| 163 | } | 162 | } |
| @@ -247,7 +246,7 @@ void USB_set_host_by_voltage(void) | |||
| 247 | 246 | ||
| 248 | SR_EXP_WriteData(); | 247 | SR_EXP_WriteData(); |
| 249 | 248 | ||
| 250 | CLK_delay_ms(250); | 249 | wait_ms(250); |
| 251 | 250 | ||
| 252 | while ((v_5v = adc_get(ADC_5V)) < ADC_5V_START_LEVEL) { DBGC(DC_USB_SET_HOST_5V_LOW_WAITING); } | 251 | while ((v_5v = adc_get(ADC_5V)) < ADC_5V_START_LEVEL) { DBGC(DC_USB_SET_HOST_5V_LOW_WAITING); } |
| 253 | 252 | ||
| @@ -313,11 +312,11 @@ uint8_t USB2422_Port_Detect_Init(void) | |||
| 313 | 312 | ||
| 314 | USB_set_host_by_voltage(); | 313 | USB_set_host_by_voltage(); |
| 315 | 314 | ||
| 316 | port_detect_retry_ms = CLK_get_ms() + PORT_DETECT_RETRY_INTERVAL; | 315 | port_detect_retry_ms = timer_read64() + PORT_DETECT_RETRY_INTERVAL; |
| 317 | 316 | ||
| 318 | while (!USB_active()) | 317 | while (!USB_active()) |
| 319 | { | 318 | { |
| 320 | tmod = CLK_get_ms() % PORT_DETECT_RETRY_INTERVAL; | 319 | tmod = timer_read64() % PORT_DETECT_RETRY_INTERVAL; |
| 321 | 320 | ||
| 322 | if (v_con_1 > v_con_2) //Values updated from USB_set_host_by_voltage(); | 321 | if (v_con_1 > v_con_2) //Values updated from USB_set_host_by_voltage(); |
| 323 | { | 322 | { |
| @@ -333,7 +332,7 @@ uint8_t USB2422_Port_Detect_Init(void) | |||
| 333 | else { DBG_LED_OFF; } | 332 | else { DBG_LED_OFF; } |
| 334 | } | 333 | } |
| 335 | 334 | ||
| 336 | if (CLK_get_ms() > port_detect_retry_ms) | 335 | if (timer_read64() > port_detect_retry_ms) |
| 337 | { | 336 | { |
| 338 | DBGC(DC_PORT_DETECT_INIT_FAILED); | 337 | DBGC(DC_PORT_DETECT_INIT_FAILED); |
| 339 | return 0; | 338 | return 0; |
