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author | Ryan <fauxpark@gmail.com> | 2020-03-06 23:55:15 +1100 |
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committer | GitHub <noreply@github.com> | 2020-03-06 23:55:15 +1100 |
commit | 9810756ee02327673456cb965612eb657700a218 (patch) | |
tree | afddba1da246567c8146a180b975578b7cd5a644 | |
parent | 918a85d342aa608deac1650ddd0692dd1717c5e3 (diff) | |
download | qmk_firmware-9810756ee02327673456cb965612eb657700a218.tar.gz qmk_firmware-9810756ee02327673456cb965612eb657700a218.zip |
Fix typo in uart.c backport and add 32A "support" (#8219)
-rw-r--r-- | tmk_core/common/uart.c | 39 |
1 files changed, 27 insertions, 12 deletions
diff --git a/tmk_core/common/uart.c b/tmk_core/common/uart.c index ccf7f7ff0..66857b673 100644 --- a/tmk_core/common/uart.c +++ b/tmk_core/common/uart.c | |||
@@ -33,7 +33,7 @@ | |||
33 | 33 | ||
34 | #if defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__) | 34 | #if defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__) |
35 | # define UDRn UDR0 | 35 | # define UDRn UDR0 |
36 | # define UBRRn UBRR0 | 36 | # define UBRRnL UBRR0L |
37 | # define UCSRnA UCSR0A | 37 | # define UCSRnA UCSR0A |
38 | # define UCSRnB UCSR0B | 38 | # define UCSRnB UCSR0B |
39 | # define UCSRnC UCSR0C | 39 | # define UCSRnC UCSR0C |
@@ -44,11 +44,11 @@ | |||
44 | # define UCSZn1 UCSZ01 | 44 | # define UCSZn1 UCSZ01 |
45 | # define UCSZn0 UCSZ00 | 45 | # define UCSZn0 UCSZ00 |
46 | # define UDRIEn UDRIE0 | 46 | # define UDRIEn UDRIE0 |
47 | # define UDRE_vect USART_UDRE_vect | 47 | # define USARTn_UDRE_vect USART_UDRE_vect |
48 | # define RX_vect USART_RX_vect | 48 | # define USARTn_RX_vect USART_RX_vect |
49 | #elif defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) | 49 | #elif defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) |
50 | # define UDRn UDR1 | 50 | # define UDRn UDR1 |
51 | # define UBRRn UBRR1 | 51 | # define UBRRnL UBRR1L |
52 | # define UCSRnA UCSR1A | 52 | # define UCSRnA UCSR1A |
53 | # define UCSRnB UCSR1B | 53 | # define UCSRnB UCSR1B |
54 | # define UCSRnC UCSR1C | 54 | # define UCSRnC UCSR1C |
@@ -59,8 +59,23 @@ | |||
59 | # define UCSZn1 UCSZ11 | 59 | # define UCSZn1 UCSZ11 |
60 | # define UCSZn0 UCSZ10 | 60 | # define UCSZn0 UCSZ10 |
61 | # define UDRIEn UDRIE1 | 61 | # define UDRIEn UDRIE1 |
62 | # define UDRE_vect USART1_UDRE_vect | 62 | # define USARTn_UDRE_vect USART1_UDRE_vect |
63 | # define RX_vect USART1_RX_vect | 63 | # define USARTn_RX_vect USART1_RX_vect |
64 | #elif defined(__AVR_ATmega32A__) | ||
65 | # define UDRn UDR | ||
66 | # define UBRRnL UBRRL | ||
67 | # define UCSRnA UCSRA | ||
68 | # define UCSRnB UCSRB | ||
69 | # define UCSRnC UCSRC | ||
70 | # define U2Xn U2X | ||
71 | # define RXENn RXEN | ||
72 | # define TXENn TXEN | ||
73 | # define RXCIEn RXCIE | ||
74 | # define UCSZn1 UCSZ1 | ||
75 | # define UCSZn0 UCSZ0 | ||
76 | # define UDRIEn UDRIE | ||
77 | # define USARTn_UDRE_vect USART_UDRE_vect | ||
78 | # define USARTn_RX_vect USART_RX_vect | ||
64 | #endif | 79 | #endif |
65 | 80 | ||
66 | // These buffers may be any size from 2 to 256 bytes. | 81 | // These buffers may be any size from 2 to 256 bytes. |
@@ -77,7 +92,7 @@ static volatile uint8_t rx_buffer_tail; | |||
77 | // Initialize the UART | 92 | // Initialize the UART |
78 | void uart_init(uint32_t baud) { | 93 | void uart_init(uint32_t baud) { |
79 | cli(); | 94 | cli(); |
80 | UBRRn = (F_CPU / 4 / baud - 1) / 2; | 95 | UBRRnL = (F_CPU / 4 / baud - 1) / 2; |
81 | UCSRnA = (1 << U2Xn); | 96 | UCSRnA = (1 << U2Xn); |
82 | UCSRnB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn); | 97 | UCSRnB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn); |
83 | UCSRnC = (1 << UCSZn1) | (1 << UCSZn0); | 98 | UCSRnC = (1 << UCSZn1) | (1 << UCSZn0); |
@@ -99,7 +114,7 @@ void uart_putchar(uint8_t c) { | |||
99 | // cli(); | 114 | // cli(); |
100 | tx_buffer[i] = c; | 115 | tx_buffer[i] = c; |
101 | tx_buffer_head = i; | 116 | tx_buffer_head = i; |
102 | UCSRB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn) | (1 << UDRIEn); | 117 | UCSRnB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn) | (1 << UDRIEn); |
103 | // sei(); | 118 | // sei(); |
104 | } | 119 | } |
105 | 120 | ||
@@ -129,7 +144,7 @@ uint8_t uart_available(void) { | |||
129 | } | 144 | } |
130 | 145 | ||
131 | // Transmit Interrupt | 146 | // Transmit Interrupt |
132 | ISR(UDRE_vect) { | 147 | ISR(USARTn_UDRE_vect) { |
133 | uint8_t i; | 148 | uint8_t i; |
134 | 149 | ||
135 | if (tx_buffer_head == tx_buffer_tail) { | 150 | if (tx_buffer_head == tx_buffer_tail) { |
@@ -138,13 +153,13 @@ ISR(UDRE_vect) { | |||
138 | } else { | 153 | } else { |
139 | i = tx_buffer_tail + 1; | 154 | i = tx_buffer_tail + 1; |
140 | if (i >= TX_BUFFER_SIZE) i = 0; | 155 | if (i >= TX_BUFFER_SIZE) i = 0; |
141 | UDR0 = tx_buffer[i]; | 156 | UDRn = tx_buffer[i]; |
142 | tx_buffer_tail = i; | 157 | tx_buffer_tail = i; |
143 | } | 158 | } |
144 | } | 159 | } |
145 | 160 | ||
146 | // Receive Interrupt | 161 | // Receive Interrupt |
147 | ISR(RX_vect) { | 162 | ISR(USARTn_RX_vect) { |
148 | uint8_t c, i; | 163 | uint8_t c, i; |
149 | 164 | ||
150 | c = UDRn; | 165 | c = UDRn; |