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author | tmk <hasu@tmk-kbd.com> | 2015-05-14 15:38:15 +0900 |
---|---|---|
committer | tmk <hasu@tmk-kbd.com> | 2015-05-19 00:39:43 +0900 |
commit | 9a2282157fbdf57ef0a50d4fea7da72505906588 (patch) | |
tree | 38bceaf7a84dcdb9678155e845520b4f5494c559 | |
parent | 6014d1014e96a7b484699d4dd8c04292c0233b0e (diff) | |
download | qmk_firmware-9a2282157fbdf57ef0a50d4fea7da72505906588.tar.gz qmk_firmware-9a2282157fbdf57ef0a50d4fea7da72505906588.zip |
ibm4704_usb: Fix interrupt of clock(rising edge)
-rw-r--r-- | converter/ibm4704_usb/config.h | 4 | ||||
-rw-r--r-- | converter/ibm4704_usb/ibm4704.txt | 6 | ||||
-rw-r--r-- | tmk_core/protocol/ibm4704.c | 39 |
3 files changed, 23 insertions, 26 deletions
diff --git a/converter/ibm4704_usb/config.h b/converter/ibm4704_usb/config.h index 4f267b3b7..d9d8d39bc 100644 --- a/converter/ibm4704_usb/config.h +++ b/converter/ibm4704_usb/config.h | |||
@@ -51,8 +51,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
51 | #define IBM4704_DATA_DDR DDRD | 51 | #define IBM4704_DATA_DDR DDRD |
52 | #define IBM4704_DATA_BIT 0 | 52 | #define IBM4704_DATA_BIT 0 |
53 | 53 | ||
54 | /* Pin interrupt on rising edge */ | 54 | /* Pin interrupt on rising edge of clock */ |
55 | #define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(0<<ISC10)); } while (0) | 55 | #define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(1<<ISC10)); } while (0) |
56 | #define IBM4704_INT_ON() do { EIMSK |= (1<<INT1); } while (0) | 56 | #define IBM4704_INT_ON() do { EIMSK |= (1<<INT1); } while (0) |
57 | #define IBM4704_INT_OFF() do { EIMSK &= ~(1<<INT1); } while (0) | 57 | #define IBM4704_INT_OFF() do { EIMSK &= ~(1<<INT1); } while (0) |
58 | #define IBM4704_INT_VECT INT1_vect | 58 | #define IBM4704_INT_VECT INT1_vect |
diff --git a/converter/ibm4704_usb/ibm4704.txt b/converter/ibm4704_usb/ibm4704.txt index 9c4895d92..50d8c98b0 100644 --- a/converter/ibm4704_usb/ibm4704.txt +++ b/converter/ibm4704_usb/ibm4704.txt | |||
@@ -57,15 +57,15 @@ Keyboard to Host | |||
57 | ---------------- | 57 | ---------------- |
58 | Data bits are LSB first and Pairty is odd. Clock has around 60us high and 30us low part. | 58 | Data bits are LSB first and Pairty is odd. Clock has around 60us high and 30us low part. |
59 | 59 | ||
60 | ____ __ __ __ __ __ __ __ __ __ ________ | 60 | ____ __ __ __ __ __ __ __ __ __ _______ |
61 | Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ | 61 | Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ |
62 | ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ | 62 | ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ |
63 | Data ____/ X____X____X____X____X____X____X____X____X____X________ | 63 | Data ____/ X____X____X____X____X____X____X____X____X____X________ |
64 | Start 0 1 2 3 4 5 6 7 P Stop | 64 | Start 0 1 2 3 4 5 6 7 P Stop |
65 | 65 | ||
66 | Start bit: can be long as 300-350us. | 66 | Start bit: can be long as 300-350us. |
67 | Inhibit: Pull Data line down to inhibit keyboard to send. | 67 | Inhibit: Pull Data line down to inhibit keyboard to send. |
68 | Timing: Host reads bit while Clock is hi. | 68 | Timing: Host reads bit while Clock is hi.(rising edge) |
69 | Stop bit: Keyboard pulls down Data line to lo after 9th clock. | 69 | Stop bit: Keyboard pulls down Data line to lo after 9th clock. |
70 | 70 | ||
71 | 71 | ||
diff --git a/tmk_core/protocol/ibm4704.c b/tmk_core/protocol/ibm4704.c index a10a5e74d..a2c670047 100644 --- a/tmk_core/protocol/ibm4704.c +++ b/tmk_core/protocol/ibm4704.c | |||
@@ -104,50 +104,47 @@ uint8_t ibm4704_recv_response(void) | |||
104 | return rbuf_dequeue(); | 104 | return rbuf_dequeue(); |
105 | } | 105 | } |
106 | 106 | ||
107 | uint8_t ibm4704_recv(void) | ||
108 | { | ||
109 | if (rbuf_has_data()) { | ||
110 | return rbuf_dequeue(); | ||
111 | } else { | ||
112 | return -1; | ||
113 | } | ||
114 | } | ||
115 | |||
107 | /* | 116 | /* |
108 | Keyboard to Host | 117 | Keyboard to Host |
109 | ---------------- | 118 | ---------------- |
110 | Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part. | 119 | Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part. |
111 | 120 | ||
112 | ____ __ __ __ __ __ __ __ __ __ ________ | 121 | ____ __ __ __ __ __ __ __ __ __ _______ |
113 | Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ | 122 | Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ |
114 | ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ | 123 | ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ |
115 | Data ____/ X____X____X____X____X____X____X____X____X____X________ | 124 | Data ____/ X____X____X____X____X____X____X____X____X____X________ |
116 | Start 0 1 2 3 4 5 6 7 P Stop | 125 | Start 0 1 2 3 4 5 6 7 P Stop |
117 | 126 | ||
118 | Start bit: can be long as 300-350us. | 127 | Start bit: can be long as 300-350us. |
119 | Inhibit: Pull Data line down to inhibit keyboard to send. | 128 | Inhibit: Pull Data line down to inhibit keyboard to send. |
120 | Timing: Host reads bit while Clock is hi. | 129 | Timing: Host reads bit while Clock is hi.(rising edge) |
121 | Stop bit: Keyboard pulls down Data line to lo after 9th clock. | 130 | Stop bit: Keyboard pulls down Data line to lo after 9th clock. |
122 | */ | 131 | */ |
123 | uint8_t ibm4704_recv(void) | ||
124 | { | ||
125 | if (rbuf_has_data()) { | ||
126 | return rbuf_dequeue(); | ||
127 | } else { | ||
128 | return -1; | ||
129 | } | ||
130 | } | ||
131 | |||
132 | ISR(IBM4704_INT_VECT) | 132 | ISR(IBM4704_INT_VECT) |
133 | { | 133 | { |
134 | static enum { | 134 | static enum { |
135 | INIT, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY, | 135 | STOP, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY |
136 | } state = INIT; | 136 | } state = STOP; |
137 | // LSB first | 137 | // LSB first |
138 | static uint8_t data = 0; | 138 | static uint8_t data = 0; |
139 | // Odd parity | 139 | // Odd parity |
140 | static uint8_t parity = false; | 140 | static uint8_t parity = false; |
141 | 141 | ||
142 | ibm4704_error = 0; | 142 | ibm4704_error = 0; |
143 | // return unless falling edge | ||
144 | if (clock_in()) { goto RETURN; } // why this occurs? | ||
145 | 143 | ||
146 | state++; | 144 | switch (state++) { |
147 | switch (state) { | 145 | case STOP: |
148 | case START: | ||
149 | // Data:Low | 146 | // Data:Low |
150 | WAIT(data_hi, 10, state); | 147 | WAIT(data_lo, 10, state); |
151 | break; | 148 | break; |
152 | case BIT0: | 149 | case BIT0: |
153 | case BIT1: | 150 | case BIT1: |
@@ -182,7 +179,7 @@ ERROR: | |||
182 | while (ibm4704_send(0xFE)) _delay_ms(1); // resend | 179 | while (ibm4704_send(0xFE)) _delay_ms(1); // resend |
183 | xprintf("R:%02X%02X\n", state, data); | 180 | xprintf("R:%02X%02X\n", state, data); |
184 | DONE: | 181 | DONE: |
185 | state = INIT; | 182 | state = STOP; |
186 | data = 0; | 183 | data = 0; |
187 | parity = false; | 184 | parity = false; |
188 | RETURN: | 185 | RETURN: |