aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorQMK Bot <hello@qmk.fm>2020-02-21 11:04:05 +0000
committerQMK Bot <hello@qmk.fm>2020-02-21 11:04:05 +0000
commita7d859dab86ee0d741559da68eee14949116fe16 (patch)
tree66eda77aa205d59af4fdde66a8d072f4c54ad21f
parent1751c3cc25ecc1734976d9790598d64133ee306d (diff)
downloadqmk_firmware-a7d859dab86ee0d741559da68eee14949116fe16.tar.gz
qmk_firmware-a7d859dab86ee0d741559da68eee14949116fe16.zip
format code according to conventions [skip ci]
-rw-r--r--tmk_core/common/uart.c62
1 files changed, 31 insertions, 31 deletions
diff --git a/tmk_core/common/uart.c b/tmk_core/common/uart.c
index 412fcf8e1..ccf7f7ff0 100644
--- a/tmk_core/common/uart.c
+++ b/tmk_core/common/uart.c
@@ -32,35 +32,35 @@
32#include "uart.h" 32#include "uart.h"
33 33
34#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__) 34#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
35# define UDRn UDR0 35# define UDRn UDR0
36# define UBRRn UBRR0 36# define UBRRn UBRR0
37# define UCSRnA UCSR0A 37# define UCSRnA UCSR0A
38# define UCSRnB UCSR0B 38# define UCSRnB UCSR0B
39# define UCSRnC UCSR0C 39# define UCSRnC UCSR0C
40# define U2Xn U2X0 40# define U2Xn U2X0
41# define RXENn RXEN0 41# define RXENn RXEN0
42# define TXENn TXEN0 42# define TXENn TXEN0
43# define RXCIEn RXCIE0 43# define RXCIEn RXCIE0
44# define UCSZn1 UCSZ01 44# define UCSZn1 UCSZ01
45# define UCSZn0 UCSZ00 45# define UCSZn0 UCSZ00
46# define UDRIEn UDRIE0 46# define UDRIEn UDRIE0
47# define UDRE_vect USART_UDRE_vect 47# define UDRE_vect USART_UDRE_vect
48# define RX_vect USART_RX_vect 48# define RX_vect USART_RX_vect
49#elif defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) 49#elif defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
50# define UDRn UDR1 50# define UDRn UDR1
51# define UBRRn UBRR1 51# define UBRRn UBRR1
52# define UCSRnA UCSR1A 52# define UCSRnA UCSR1A
53# define UCSRnB UCSR1B 53# define UCSRnB UCSR1B
54# define UCSRnC UCSR1C 54# define UCSRnC UCSR1C
55# define U2Xn U2X1 55# define U2Xn U2X1
56# define RXENn RXEN1 56# define RXENn RXEN1
57# define TXENn TXEN1 57# define TXENn TXEN1
58# define RXCIEn RXCIE1 58# define RXCIEn RXCIE1
59# define UCSZn1 UCSZ11 59# define UCSZn1 UCSZ11
60# define UCSZn0 UCSZ10 60# define UCSZn0 UCSZ10
61# define UDRIEn UDRIE1 61# define UDRIEn UDRIE1
62# define UDRE_vect USART1_UDRE_vect 62# define UDRE_vect USART1_UDRE_vect
63# define RX_vect USART1_RX_vect 63# define RX_vect USART1_RX_vect
64#endif 64#endif
65 65
66// These buffers may be any size from 2 to 256 bytes. 66// These buffers may be any size from 2 to 256 bytes.
@@ -92,14 +92,14 @@ void uart_putchar(uint8_t c) {
92 92
93 i = tx_buffer_head + 1; 93 i = tx_buffer_head + 1;
94 if (i >= TX_BUFFER_SIZE) i = 0; 94 if (i >= TX_BUFFER_SIZE) i = 0;
95 // return immediately to avoid deadlock when interrupt is disabled(called from ISR) 95 // return immediately to avoid deadlock when interrupt is disabled(called from ISR)
96 if (tx_buffer_tail == i && (SREG & (1<<SREG_I)) == 0) return; 96 if (tx_buffer_tail == i && (SREG & (1 << SREG_I)) == 0) return;
97 while (tx_buffer_tail == i) 97 while (tx_buffer_tail == i)
98 ; // wait until space in buffer 98 ; // wait until space in buffer
99 // cli(); 99 // cli();
100 tx_buffer[i] = c; 100 tx_buffer[i] = c;
101 tx_buffer_head = i; 101 tx_buffer_head = i;
102 UCSRB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn) | (1 << UDRIEn); 102 UCSRB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn) | (1 << UDRIEn);
103 // sei(); 103 // sei();
104} 104}
105 105