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| author | ishtob <ishtob@gmail.com> | 2018-12-04 11:04:57 -0500 |
|---|---|---|
| committer | Drashna Jaelre <drashna@live.com> | 2018-12-04 08:04:57 -0800 |
| commit | 4099536c0e7a099b181a80e483b4b95f389b5a7e (patch) | |
| tree | 311c8a15013cce5ee9275fe8654c9b52dc9ca1e2 /drivers/haptic/DRV2605L.h | |
| parent | 4bb28d2df092408a7a0e32a8d8ab47b7f4008fcd (diff) | |
| download | qmk_firmware-4099536c0e7a099b181a80e483b4b95f389b5a7e.tar.gz qmk_firmware-4099536c0e7a099b181a80e483b4b95f389b5a7e.zip | |
adding Hadron v3 keyboard, QWIIC devices support, haptic feedback support (#4462)
* add initial support for hadron ver3
* add initial support for hadron ver3
* pull qwiic support for micro_led to be modified for use in hadron's 64x24 ssd1306 oled display
* initial work on OLED using qwiic driver
* early work to get 128x32 oled working by redefining qwiic micro oled parameters. Currently working, but would affect qwiic's micro oled functionality
* moved oled defines to config.h and added ifndef to micro_oled driver
* WORKING :D - note, still work in progress to get the start location correct on the 128x32 display.
* added equation to automatically calculate display offset based on screen width
* adding time-out timer to oled display
* changed read lock staus via read_led_state
* lock indications fixes
* Added scroll lock indication to oled
* add support for DRV2605 haptic driver
* Improve readabiity of DRV2605 driver.
-added typedef for waveform library
-added unions for registers
* Update keyboards/hadron/ver2/keymaps/default/config.h
Co-Authored-By: ishtob <ishtob@gmail.com>
* Update keyboards/hadron/ver2/keymaps/default/config.h
Co-Authored-By: ishtob <ishtob@gmail.com>
* Update keyboards/hadron/ver2/keymaps/default/config.h
Co-Authored-By: ishtob <ishtob@gmail.com>
* Update keyboards/hadron/ver2/keymaps/default/config.h
Co-Authored-By: ishtob <ishtob@gmail.com>
* Fixes for PR
* PR fixes
* fix old persistent layer function to use new set_single_persistent_default_layer
* fix issues with changing makefile defines that broken per-key haptic pulse
* Comment fixes
* Add definable parameter and auto-calibration based on motor choice
Diffstat (limited to 'drivers/haptic/DRV2605L.h')
| -rw-r--r-- | drivers/haptic/DRV2605L.h | 394 |
1 files changed, 394 insertions, 0 deletions
diff --git a/drivers/haptic/DRV2605L.h b/drivers/haptic/DRV2605L.h new file mode 100644 index 000000000..de9d294e9 --- /dev/null +++ b/drivers/haptic/DRV2605L.h | |||
| @@ -0,0 +1,394 @@ | |||
| 1 | /* Copyright 2018 ishtob | ||
| 2 | * Driver for DRV2605L written for QMK | ||
| 3 | * | ||
| 4 | * This program is free software: you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation, either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #pragma once | ||
| 19 | #include "i2c_master.h" | ||
| 20 | |||
| 21 | /* Initialization settings | ||
| 22 | |||
| 23 | * Feedback Control Settings */ | ||
| 24 | #ifndef FB_ERM_LRA | ||
| 25 | #define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/ | ||
| 26 | #endif | ||
| 27 | #ifndef FB_BRAKEFACTOR | ||
| 28 | #define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */ | ||
| 29 | #endif | ||
| 30 | #ifndef FB_LOOPGAIN | ||
| 31 | #define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */ | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #ifndef RATED_VOLTAGE | ||
| 35 | #define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */ | ||
| 36 | #ifndef V_PEAK | ||
| 37 | #define V_PEAK 2.8 | ||
| 38 | #endif | ||
| 39 | #endif | ||
| 40 | |||
| 41 | /* LRA specific settings */ | ||
| 42 | #if FB_ERM_LRA == 1 | ||
| 43 | #ifndef V_RMS | ||
| 44 | #define V_RMS 2.0 | ||
| 45 | #endif | ||
| 46 | #ifndef V_PEAK | ||
| 47 | #define V_PEAK 2.1 | ||
| 48 | #endif | ||
| 49 | #ifndef F_LRA | ||
| 50 | #define F_LRA 205 | ||
| 51 | #endif | ||
| 52 | #endif | ||
| 53 | |||
| 54 | /* Library Selection */ | ||
| 55 | #ifndef LIB_SELECTION | ||
| 56 | #if FB_ERM_LRA == 1 | ||
| 57 | #define LIB_SELECTION 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */ | ||
| 58 | #else | ||
| 59 | #define LIB_SELECTION 1 | ||
| 60 | #endif | ||
| 61 | #endif | ||
| 62 | |||
| 63 | /* Control 1 register settings */ | ||
| 64 | #ifndef DRIVE_TIME | ||
| 65 | #define DRIVE_TIME 25 | ||
| 66 | #endif | ||
| 67 | #ifndef AC_COUPLE | ||
| 68 | #define AC_COUPLE 0 | ||
| 69 | #endif | ||
| 70 | #ifndef STARTUP_BOOST | ||
| 71 | #define STARTUP_BOOST 1 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* Control 2 Settings */ | ||
| 75 | #ifndef BIDIR_INPUT | ||
| 76 | #define BIDIR_INPUT 1 | ||
| 77 | #endif | ||
| 78 | #ifndef BRAKE_STAB | ||
| 79 | #define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */ | ||
| 80 | #endif | ||
| 81 | #ifndef SAMPLE_TIME | ||
| 82 | #define SAMPLE_TIME 3 | ||
| 83 | #endif | ||
| 84 | #ifndef BLANKING_TIME | ||
| 85 | #define BLANKING_TIME 1 | ||
| 86 | #endif | ||
| 87 | #ifndef IDISS_TIME | ||
| 88 | #define IDISS_TIME 1 | ||
| 89 | #endif | ||
| 90 | |||
| 91 | /* Control 3 settings */ | ||
| 92 | #ifndef NG_THRESH | ||
| 93 | #define NG_THRESH 2 | ||
| 94 | #endif | ||
| 95 | #ifndef ERM_OPEN_LOOP | ||
| 96 | #define ERM_OPEN_LOOP 1 | ||
| 97 | #endif | ||
| 98 | #ifndef SUPPLY_COMP_DIS | ||
| 99 | #define SUPPLY_COMP_DIS 0 | ||
| 100 | #endif | ||
| 101 | #ifndef DATA_FORMAT_RTO | ||
| 102 | #define DATA_FORMAT_RTO 0 | ||
| 103 | #endif | ||
| 104 | #ifndef LRA_DRIVE_MODE | ||
| 105 | #define LRA_DRIVE_MODE 0 | ||
| 106 | #endif | ||
| 107 | #ifndef N_PWM_ANALOG | ||
| 108 | #define N_PWM_ANALOG 0 | ||
| 109 | #endif | ||
| 110 | #ifndef LRA_OPEN_LOOP | ||
| 111 | #define LRA_OPEN_LOOP 0 | ||
| 112 | #endif | ||
| 113 | |||
| 114 | /* Control 4 settings */ | ||
| 115 | #ifndef ZC_DET_TIME | ||
| 116 | #define ZC_DET_TIME 0 | ||
| 117 | #endif | ||
| 118 | #ifndef AUTO_CAL_TIME | ||
| 119 | #define AUTO_CAL_TIME 3 | ||
| 120 | #endif | ||
| 121 | |||
| 122 | /* register defines -------------------------------------------------------- */ | ||
| 123 | #define DRV2605L_BASE_ADDRESS 0x5A /* DRV2605L Base address */ | ||
| 124 | #define DRV_STATUS 0x00 | ||
| 125 | #define DRV_MODE 0x01 | ||
| 126 | #define DRV_RTP_INPUT 0x02 | ||
| 127 | #define DRV_LIB_SELECTION 0x03 | ||
| 128 | #define DRV_WAVEFORM_SEQ_1 0x04 | ||
| 129 | #define DRV_WAVEFORM_SEQ_2 0x05 | ||
| 130 | #define DRV_WAVEFORM_SEQ_3 0x06 | ||
| 131 | #define DRV_WAVEFORM_SEQ_4 0x07 | ||
| 132 | #define DRV_WAVEFORM_SEQ_5 0x08 | ||
| 133 | #define DRV_WAVEFORM_SEQ_6 0x09 | ||
| 134 | #define DRV_WAVEFORM_SEQ_7 0x0A | ||
| 135 | #define DRV_WAVEFORM_SEQ_8 0x0B | ||
| 136 | #define DRV_GO 0x0C | ||
| 137 | #define DRV_OVERDRIVE_TIME_OFFSET 0x0D | ||
| 138 | #define DRV_SUSTAIN_TIME_OFFSET_P 0x0E | ||
| 139 | #define DRV_SUSTAIN_TIME_OFFSET_N 0x0F | ||
| 140 | #define DRV_BRAKE_TIME_OFFSET 0x10 | ||
| 141 | #define DRV_AUDIO_2_VIBE_CTRL 0x11 | ||
| 142 | #define DRV_AUDIO_2_VIBE_MIN_IN 0x12 | ||
| 143 | #define DRV_AUDIO_2_VIBE_MAX_IN 0x13 | ||
| 144 | #define DRV_AUDIO_2_VIBE_MIN_OUTDRV 0x14 | ||
| 145 | #define DRV_AUDIO_2_VIBE_MAX_OUTDRV 0x15 | ||
| 146 | #define DRV_RATED_VOLT 0x16 | ||
| 147 | #define DRV_OVERDRIVE_CLAMP_VOLT 0x17 | ||
| 148 | #define DRV_AUTO_CALIB_COMP_RESULT 0x18 | ||
| 149 | #define DRV_AUTO_CALIB_BEMF_RESULT 0x19 | ||
| 150 | #define DRV_FEEDBACK_CTRL 0x1A | ||
| 151 | #define DRV_CTRL_1 0x1B | ||
| 152 | #define DRV_CTRL_2 0x1C | ||
| 153 | #define DRV_CTRL_3 0x1D | ||
| 154 | #define DRV_CTRL_4 0x1E | ||
| 155 | #define DRV_CTRL_5 0x1F | ||
| 156 | #define DRV_OPEN_LOOP_PERIOD 0x20 | ||
| 157 | #define DRV_VBAT_VOLT_MONITOR 0x21 | ||
| 158 | #define DRV_LRA_RESONANCE_PERIOD 0x22 | ||
| 159 | |||
| 160 | void DRV_init(void); | ||
| 161 | void DRV_write(const uint8_t drv_register, const uint8_t settings); | ||
| 162 | uint8_t DRV_read(const uint8_t regaddress); | ||
| 163 | void DRV_pulse(const uint8_t sequence); | ||
| 164 | |||
| 165 | |||
| 166 | typedef enum DRV_EFFECT{ | ||
| 167 | clear_sequence = 0, | ||
| 168 | strong_click = 1, | ||
| 169 | strong_click_60 = 2, | ||
| 170 | strong_click_30 = 3, | ||
| 171 | sharp_click = 4, | ||
| 172 | sharp_click_60 = 5, | ||
| 173 | sharp_click_30 = 6, | ||
| 174 | soft_bump = 7, | ||
| 175 | soft_bump_60 = 8, | ||
| 176 | soft_bump_30 = 9, | ||
| 177 | dbl_click = 10, | ||
| 178 | dbl_click_60 = 11, | ||
| 179 | trp_click = 12, | ||
| 180 | soft_fuzz = 13, | ||
| 181 | strong_buzz = 14, | ||
| 182 | alert_750ms = 15, | ||
| 183 | alert_1000ms = 16, | ||
| 184 | strong_click1 = 17, | ||
| 185 | strong_click2_80 = 18, | ||
| 186 | strong_click3_60 = 19, | ||
| 187 | strong_click4_30 = 20, | ||
| 188 | medium_click1 = 21, | ||
| 189 | medium_click2_80 = 22, | ||
| 190 | medium_click3_60 = 23, | ||
| 191 | sharp_tick1 = 24, | ||
| 192 | sharp_tick2_80 = 25, | ||
| 193 | sharp_tick3_60 = 26, | ||
| 194 | sh_dblclick_str = 27, | ||
| 195 | sh_dblclick_str_80 = 28, | ||
| 196 | sh_dblclick_str_60 = 29, | ||
| 197 | sh_dblclick_str_30 = 30, | ||
| 198 | sh_dblclick_med = 31, | ||
| 199 | sh_dblclick_med_80 = 32, | ||
| 200 | sh_dblclick_med_60 = 33, | ||
| 201 | sh_dblsharp_tick = 34, | ||
| 202 | sh_dblsharp_tick_80 = 35, | ||
| 203 | sh_dblsharp_tick_60 = 36, | ||
| 204 | lg_dblclick_str = 37, | ||
| 205 | lg_dblclick_str_80 = 38, | ||
| 206 | lg_dblclick_str_60 = 39, | ||
| 207 | lg_dblclick_str_30 = 40, | ||
| 208 | lg_dblclick_med = 41, | ||
| 209 | lg_dblclick_med_80 = 42, | ||
| 210 | lg_dblclick_med_60 = 43, | ||
| 211 | lg_dblsharp_tick = 44, | ||
| 212 | lg_dblsharp_tick_80 = 45, | ||
| 213 | lg_dblsharp_tick_60 = 46, | ||
| 214 | buzz = 47, | ||
| 215 | buzz_80 = 48, | ||
| 216 | buzz_60 = 49, | ||
| 217 | buzz_40 = 50, | ||
| 218 | buzz_20 = 51, | ||
| 219 | pulsing_strong = 52, | ||
| 220 | pulsing_strong_80 = 53, | ||
| 221 | pulsing_medium = 54, | ||
| 222 | pulsing_medium_80 = 55, | ||
| 223 | pulsing_sharp = 56, | ||
| 224 | pulsing_sharp_80 = 57, | ||
| 225 | transition_click = 58, | ||
| 226 | transition_click_80 = 59, | ||
| 227 | transition_click_60 = 60, | ||
| 228 | transition_click_40 = 61, | ||
| 229 | transition_click_20 = 62, | ||
| 230 | transition_click_10 = 63, | ||
| 231 | transition_hum = 64, | ||
| 232 | transition_hum_80 = 65, | ||
| 233 | transition_hum_60 = 66, | ||
| 234 | transition_hum_40 = 67, | ||
| 235 | transition_hum_20 = 68, | ||
| 236 | transition_hum_10 = 69, | ||
| 237 | transition_rampdown_long_smooth1 = 70, | ||
| 238 | transition_rampdown_long_smooth2 = 71, | ||
| 239 | transition_rampdown_med_smooth1 = 72, | ||
| 240 | transition_rampdown_med_smooth2 = 73, | ||
| 241 | transition_rampdown_short_smooth1 = 74, | ||
| 242 | transition_rampdown_short_smooth2 = 75, | ||
| 243 | transition_rampdown_long_sharp1 = 76, | ||
| 244 | transition_rampdown_long_sharp2 = 77, | ||
| 245 | transition_rampdown_med_sharp1 = 78, | ||
| 246 | transition_rampdown_med_sharp2 = 79, | ||
| 247 | transition_rampdown_short_sharp1 = 80, | ||
| 248 | transition_rampdown_short_sharp2 = 81, | ||
| 249 | transition_rampup_long_smooth1 = 82, | ||
| 250 | transition_rampup_long_smooth2 = 83, | ||
| 251 | transition_rampup_med_smooth1 = 84, | ||
| 252 | transition_rampup_med_smooth2 = 85, | ||
| 253 | transition_rampup_short_smooth1 = 86, | ||
| 254 | transition_rampup_short_smooth2 = 87, | ||
| 255 | transition_rampup_long_sharp1 = 88, | ||
| 256 | transition_rampup_long_sharp2 = 89, | ||
| 257 | transition_rampup_med_sharp1 = 90, | ||
| 258 | transition_rampup_med_sharp2 = 91, | ||
| 259 | transition_rampup_short_sharp1 = 92, | ||
| 260 | transition_rampup_short_sharp2 = 93, | ||
| 261 | transition_rampdown_long_smooth1_50 = 94, | ||
| 262 | transition_rampdown_long_smooth2_50 = 95, | ||
| 263 | transition_rampdown_med_smooth1_50 = 96, | ||
| 264 | transition_rampdown_med_smooth2_50 = 97, | ||
| 265 | transition_rampdown_short_smooth1_50 = 98, | ||
| 266 | transition_rampdown_short_smooth2_50 = 99, | ||
| 267 | transition_rampdown_long_sharp1_50 = 100, | ||
| 268 | transition_rampdown_long_sharp2_50 = 101, | ||
| 269 | transition_rampdown_med_sharp1_50 = 102, | ||
| 270 | transition_rampdown_med_sharp2_50 = 103, | ||
| 271 | transition_rampdown_short_sharp1_50 = 104, | ||
| 272 | transition_rampdown_short_sharp2_50 = 105, | ||
| 273 | transition_rampup_long_smooth1_50 = 106, | ||
| 274 | transition_rampup_long_smooth2_50 = 107, | ||
| 275 | transition_rampup_med_smooth1_50 = 108, | ||
| 276 | transition_rampup_med_smooth2_50 = 109, | ||
| 277 | transition_rampup_short_smooth1_50 = 110, | ||
| 278 | transition_rampup_short_smooth2_50 = 111, | ||
| 279 | transition_rampup_long_sharp1_50 = 112, | ||
| 280 | transition_rampup_long_sharp2_50 = 113, | ||
| 281 | transition_rampup_med_sharp1_50 = 114, | ||
| 282 | transition_rampup_med_sharp2_50 = 115, | ||
| 283 | transition_rampup_short_sharp1_50 = 116, | ||
| 284 | transition_rampup_short_sharp2_50 = 117, | ||
| 285 | long_buzz_for_programmatic_stopping = 118, | ||
| 286 | smooth_hum1_50 = 119, | ||
| 287 | smooth_hum2_40 = 120, | ||
| 288 | smooth_hum3_30 = 121, | ||
| 289 | smooth_hum4_20 = 122, | ||
| 290 | smooth_hum5_10 = 123, | ||
| 291 | } DRV_EFFECT; | ||
| 292 | |||
| 293 | /* Register bit array unions */ | ||
| 294 | |||
| 295 | typedef union DRVREG_STATUS { /* register 0x00 */ | ||
| 296 | uint8_t Byte; | ||
| 297 | struct { | ||
| 298 | uint8_t OC_DETECT :1; /* set to 1 when overcurrent event is detected */ | ||
| 299 | uint8_t OVER_TEMP :1; /* set to 1 when device exceeds temp threshold */ | ||
| 300 | uint8_t FB_STS :1; /* set to 1 when feedback controller has timed out */ | ||
| 301 | /* auto-calibration routine and diagnostic result | ||
| 302 | * result | auto-calibation | diagnostic | | ||
| 303 | * 0 | passed | actuator func normal | | ||
| 304 | * 1 | failed | actuator func fault* | | ||
| 305 | * * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */ | ||
| 306 | uint8_t DIAG_RESULT :1; | ||
| 307 | uint8_t :1; | ||
| 308 | uint8_t DEVICE_ID :3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */ | ||
| 309 | } Bits; | ||
| 310 | } DRVREG_STATUS; | ||
| 311 | |||
| 312 | typedef union DRVREG_MODE { /* register 0x01 */ | ||
| 313 | uint8_t Byte; | ||
| 314 | struct { | ||
| 315 | uint8_t MODE :3; /* Mode setting */ | ||
| 316 | uint8_t :3; | ||
| 317 | uint8_t STANDBY :1; /* 0:standby 1:ready */ | ||
| 318 | } Bits; | ||
| 319 | } DRVREG_MODE; | ||
| 320 | |||
| 321 | typedef union DRVREG_WAIT { | ||
| 322 | uint8_t Byte; | ||
| 323 | struct { | ||
| 324 | uint8_t WAIT_MODE :1; /* Set to 1 to interpret as wait for next 7 bits x10ms */ | ||
| 325 | uint8_t WAIT_TIME :7; | ||
| 326 | } Bits; | ||
| 327 | } DRVREG_WAIT; | ||
| 328 | |||
| 329 | typedef union DRVREG_FBR{ /* register 0x1A */ | ||
| 330 | uint8_t Byte; | ||
| 331 | struct { | ||
| 332 | uint8_t BEMF_GAIN :2; | ||
| 333 | uint8_t LOOP_GAIN :2; | ||
| 334 | uint8_t BRAKE_FACTOR :3; | ||
| 335 | uint8_t ERM_LRA :1; | ||
| 336 | } Bits; | ||
| 337 | } DRVREG_FBR; | ||
| 338 | |||
| 339 | typedef union DRVREG_CTRL1{ /* register 0x1B */ | ||
| 340 | uint8_t Byte; | ||
| 341 | struct { | ||
| 342 | uint8_t C1_DRIVE_TIME :5; | ||
| 343 | uint8_t C1_AC_COUPLE :1; | ||
| 344 | uint8_t :1; | ||
| 345 | uint8_t C1_STARTUP_BOOST :1; | ||
| 346 | } Bits; | ||
| 347 | } DRVREG_CTRL1; | ||
| 348 | |||
| 349 | typedef union DRVREG_CTRL2{ /* register 0x1C */ | ||
| 350 | uint8_t Byte; | ||
| 351 | struct { | ||
| 352 | uint8_t C2_IDISS_TIME :2; | ||
| 353 | uint8_t C2_BLANKING_TIME :2; | ||
| 354 | uint8_t C2_SAMPLE_TIME :2; | ||
| 355 | uint8_t C2_BRAKE_STAB :1; | ||
| 356 | uint8_t C2_BIDIR_INPUT :1; | ||
| 357 | } Bits; | ||
| 358 | } DRVREG_CTRL2; | ||
| 359 | |||
| 360 | typedef union DRVREG_CTRL3{ /* register 0x1D */ | ||
| 361 | uint8_t Byte; | ||
| 362 | struct { | ||
| 363 | uint8_t C3_LRA_OPEN_LOOP :1; | ||
| 364 | uint8_t C3_N_PWM_ANALOG :1; | ||
| 365 | uint8_t C3_LRA_DRIVE_MODE :1; | ||
| 366 | uint8_t C3_DATA_FORMAT_RTO :1; | ||
| 367 | uint8_t C3_SUPPLY_COMP_DIS :1; | ||
| 368 | uint8_t C3_ERM_OPEN_LOOP :1; | ||
| 369 | uint8_t C3_NG_THRESH :2; | ||
| 370 | } Bits; | ||
| 371 | } DRVREG_CTRL3; | ||
| 372 | |||
| 373 | typedef union DRVREG_CTRL4{ /* register 0x1E */ | ||
| 374 | uint8_t Byte; | ||
| 375 | struct { | ||
| 376 | uint8_t C4_OTP_PROGRAM :1; | ||
| 377 | uint8_t :1; | ||
| 378 | uint8_t C4_OTP_STATUS :1; | ||
| 379 | uint8_t :1; | ||
| 380 | uint8_t C4_AUTO_CAL_TIME :2; | ||
| 381 | uint8_t C4_ZC_DET_TIME :2; | ||
| 382 | } Bits; | ||
| 383 | } DRVREG_CTRL4; | ||
| 384 | |||
| 385 | typedef union DRVREG_CTRL5{ /* register 0x1F */ | ||
| 386 | uint8_t Byte; | ||
| 387 | struct { | ||
| 388 | uint8_t C5_IDISS_TIME :2; | ||
| 389 | uint8_t C5_BLANKING_TIME :2; | ||
| 390 | uint8_t C5_PLAYBACK_INTERVAL :1; | ||
| 391 | uint8_t C5_LRA_AUTO_OPEN_LOOP :1; | ||
| 392 | uint8_t C5_AUTO_OL_CNT :2; | ||
| 393 | } Bits; | ||
| 394 | } DRVREG_CTRL5; \ No newline at end of file | ||
