diff options
| author | yiancar <yiangosyiangou@cytanet.com.cy> | 2019-10-31 16:19:57 +0000 |
|---|---|---|
| committer | Yan-Fa Li <yanfali@gmail.com> | 2019-10-31 09:19:57 -0700 |
| commit | 1acafc94f40154db009d5ed55bca204c2399c0a8 (patch) | |
| tree | 0d0586340850d392ab59b30d806684386914fd93 /drivers | |
| parent | 2ce6adff2b0b4f049b3bd8b4169cda977c057fa5 (diff) | |
| download | qmk_firmware-1acafc94f40154db009d5ed55bca204c2399c0a8.tar.gz qmk_firmware-1acafc94f40154db009d5ed55bca204c2399c0a8.zip | |
Correct ARM STM32 I2C frequency. (#7080)
It was beleaved that this setting result in a 400Khz I2C bus.
This was incorrect, actual frequency measure with a logic analyzer was around 150Khz.
This is derived from the excel sheet linked in the .h file.
Also confirmed with the ST IDE.
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/arm/i2c_master.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h index b40fa0a91..a8ed66403 100644 --- a/drivers/arm/i2c_master.h +++ b/drivers/arm/i2c_master.h | |||
| @@ -73,19 +73,19 @@ | |||
| 73 | // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock | 73 | // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock |
| 74 | // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html | 74 | // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html |
| 75 | # ifndef I2C1_TIMINGR_PRESC | 75 | # ifndef I2C1_TIMINGR_PRESC |
| 76 | # define I2C1_TIMINGR_PRESC 15U | 76 | # define I2C1_TIMINGR_PRESC 0U |
| 77 | # endif | 77 | # endif |
| 78 | # ifndef I2C1_TIMINGR_SCLDEL | 78 | # ifndef I2C1_TIMINGR_SCLDEL |
| 79 | # define I2C1_TIMINGR_SCLDEL 4U | 79 | # define I2C1_TIMINGR_SCLDEL 7U |
| 80 | # endif | 80 | # endif |
| 81 | # ifndef I2C1_TIMINGR_SDADEL | 81 | # ifndef I2C1_TIMINGR_SDADEL |
| 82 | # define I2C1_TIMINGR_SDADEL 2U | 82 | # define I2C1_TIMINGR_SDADEL 0U |
| 83 | # endif | 83 | # endif |
| 84 | # ifndef I2C1_TIMINGR_SCLH | 84 | # ifndef I2C1_TIMINGR_SCLH |
| 85 | # define I2C1_TIMINGR_SCLH 15U | 85 | # define I2C1_TIMINGR_SCLH 38U |
| 86 | # endif | 86 | # endif |
| 87 | # ifndef I2C1_TIMINGR_SCLL | 87 | # ifndef I2C1_TIMINGR_SCLL |
| 88 | # define I2C1_TIMINGR_SCLL 21U | 88 | # define I2C1_TIMINGR_SCLL 129U |
| 89 | # endif | 89 | # endif |
| 90 | #endif | 90 | #endif |
| 91 | 91 | ||