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authoryulei <yuleiz@gmail.com>2019-12-13 09:20:04 +0800
committerDrashna Jaelre <drashna@live.com>2019-12-12 17:20:04 -0800
commita037cedfdc0bdb5737586ab4b4ef7086e53029b7 (patch)
treef80062c92eb354ea4b4281af9d95a06b23ad37f5 /drivers
parentdf78593b1ba800223c049f3f61df6ad4bf4abe7c (diff)
downloadqmk_firmware-a037cedfdc0bdb5737586ab4b4ef7086e53029b7.tar.gz
qmk_firmware-a037cedfdc0bdb5737586ab4b4ef7086e53029b7.zip
fixed I2C driver support for stm32f4 (#7526)
* correct i2c driver for stm32f4 * update pin mode definitions * update macro definition
Diffstat (limited to 'drivers')
-rw-r--r--drivers/arm/i2c_master.c2
-rw-r--r--drivers/arm/i2c_master.h24
2 files changed, 16 insertions, 10 deletions
diff --git a/drivers/arm/i2c_master.c b/drivers/arm/i2c_master.c
index 2a43ba239..b9eff0ad2 100644
--- a/drivers/arm/i2c_master.c
+++ b/drivers/arm/i2c_master.c
@@ -62,7 +62,7 @@ __attribute__((weak)) void i2c_init(void) {
62 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT); 62 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
63 63
64 chThdSleepMilliseconds(10); 64 chThdSleepMilliseconds(10);
65#ifdef USE_I2CV1 65#if defined(USE_GPIOV1)
66 palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); 66 palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
67 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); 67 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
68#else 68#else
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index efe3909a6..31cbfb977 100644
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -27,7 +27,7 @@
27#include "ch.h" 27#include "ch.h"
28#include <hal.h> 28#include <hal.h>
29 29
30#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx) 30#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F4XX) || defined(STM32L0xx) || defined(STM32L1xx)
31# define USE_I2CV1 31# define USE_I2CV1
32#endif 32#endif
33 33
@@ -51,6 +51,20 @@
51# define I2C1_SDA 7 51# define I2C1_SDA 7
52#endif 52#endif
53 53
54#if defined(STM32F1XX) || defined(STM32F1xx)
55# define USE_GPIOV1
56#endif
57
58#ifndef USE_GPIOV1
59// The default PAL alternate modes are used to signal that the pins are used for I2C
60# ifndef I2C1_SCL_PAL_MODE
61# define I2C1_SCL_PAL_MODE 4
62# endif
63# ifndef I2C1_SDA_PAL_MODE
64# define I2C1_SDA_PAL_MODE 4
65# endif
66#endif
67
54#ifdef USE_I2CV1 68#ifdef USE_I2CV1
55# ifndef I2C1_OPMODE 69# ifndef I2C1_OPMODE
56# define I2C1_OPMODE OPMODE_I2C 70# define I2C1_OPMODE OPMODE_I2C
@@ -62,14 +76,6 @@
62# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */ 76# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
63# endif 77# endif
64#else 78#else
65// The default PAL alternate modes are used to signal that the pins are used for I2C
66# ifndef I2C1_SCL_PAL_MODE
67# define I2C1_SCL_PAL_MODE 4
68# endif
69# ifndef I2C1_SDA_PAL_MODE
70# define I2C1_SDA_PAL_MODE 4
71# endif
72
73// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock 79// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
74// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html 80// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
75# ifndef I2C1_TIMINGR_PRESC 81# ifndef I2C1_TIMINGR_PRESC