aboutsummaryrefslogtreecommitdiff
path: root/quantum/config_common.h
diff options
context:
space:
mode:
authorRyan <fauxpark@gmail.com>2020-09-27 20:33:03 +1000
committerGitHub <noreply@github.com>2020-09-27 20:33:03 +1000
commit70fce6564fe691912387d09344efa1d1ce5b949e (patch)
tree42d9b87a3c1c2f22ca2722645c946a96bcad4795 /quantum/config_common.h
parent28ff51175b6d45ce5a8dbfe7ed6e7a12df3bc8a8 (diff)
downloadqmk_firmware-70fce6564fe691912387d09344efa1d1ce5b949e.tar.gz
qmk_firmware-70fce6564fe691912387d09344efa1d1ce5b949e.zip
Add logic for AT90USBxx7 where needed (#10203)
Diffstat (limited to 'quantum/config_common.h')
-rw-r--r--quantum/config_common.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/quantum/config_common.h b/quantum/config_common.h
index 84edc4639..c1e6698e5 100644
--- a/quantum/config_common.h
+++ b/quantum/config_common.h
@@ -44,7 +44,7 @@
44# define PINB_ADDRESS 0x3 44# define PINB_ADDRESS 0x3
45# define PINC_ADDRESS 0x6 45# define PINC_ADDRESS 0x6
46# define PIND_ADDRESS 0x9 46# define PIND_ADDRESS 0x9
47# elif defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB646__) 47# elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
48# define ADDRESS_BASE 0x00 48# define ADDRESS_BASE 0x00
49# define PINA_ADDRESS 0x0 49# define PINA_ADDRESS 0x0
50# define PINB_ADDRESS 0x3 50# define PINB_ADDRESS 0x3
@@ -307,7 +307,7 @@
307 UCSR1C = _BV(UCSZ11) | _BV(UCSZ10); \ 307 UCSR1C = _BV(UCSZ11) | _BV(UCSZ10); \
308 sei(); \ 308 sei(); \
309 } while (0) 309 } while (0)
310# elif (defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)) 310# elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
311# define SERIAL_UART_BAUD 115200 311# define SERIAL_UART_BAUD 115200
312# define SERIAL_UART_DATA UDR1 312# define SERIAL_UART_DATA UDR1
313/* UBRR should result in ~16 and set UCSR1A = _BV(U2X1) as per rn42 documentation. HC05 needs baudrate configured accordingly */ 313/* UBRR should result in ~16 and set UCSR1A = _BV(U2X1) as per rn42 documentation. HC05 needs baudrate configured accordingly */