diff options
| author | Damien <Dbroqua@users.noreply.github.com> | 2017-01-26 09:05:55 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-01-26 09:05:55 +0100 |
| commit | b7b94bfb132aa5f2f79b587fcfa6b1197485db27 (patch) | |
| tree | 4cae966728b7b6baf101a7ab2b95eeff16cce141 /tmk_core/common/avr | |
| parent | f91f0a715d51286064bfe808b0d463878a6d3588 (diff) | |
| parent | aac7c0aa4db6b27f4c8d8f3849f8fd41f07e892a (diff) | |
| download | qmk_firmware-b7b94bfb132aa5f2f79b587fcfa6b1197485db27.tar.gz qmk_firmware-b7b94bfb132aa5f2f79b587fcfa6b1197485db27.zip | |
Merge pull request #17 from qmk/master
Merged from QMK project
Diffstat (limited to 'tmk_core/common/avr')
| -rw-r--r-- | tmk_core/common/avr/bootloader.c | 12 | ||||
| -rw-r--r-- | tmk_core/common/avr/timer.c | 33 |
2 files changed, 36 insertions, 9 deletions
diff --git a/tmk_core/common/avr/bootloader.c b/tmk_core/common/avr/bootloader.c index ad547b985..34db8d0b0 100644 --- a/tmk_core/common/avr/bootloader.c +++ b/tmk_core/common/avr/bootloader.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | #include <stdint.h> | 1 | #include <stdint.h> |
| 2 | #include <stdbool.h> | 2 | #include <stdbool.h> |
| 3 | #include <avr/io.h> | 3 | #include <avr/io.h> |
| 4 | #include <avr/eeprom.h> | ||
| 4 | #include <avr/interrupt.h> | 5 | #include <avr/interrupt.h> |
| 5 | #include <avr/wdt.h> | 6 | #include <avr/wdt.h> |
| 6 | #include <util/delay.h> | 7 | #include <util/delay.h> |
| @@ -89,6 +90,12 @@ void bootloader_jump(void) { | |||
| 89 | _delay_ms(5); | 90 | _delay_ms(5); |
| 90 | #endif | 91 | #endif |
| 91 | 92 | ||
| 93 | #ifdef BOOTLOADHID_BOOTLOADER | ||
| 94 | // force bootloadHID to stay in bootloader mode, so that it waits | ||
| 95 | // for a new firmware to be flashed | ||
| 96 | eeprom_write_byte((uint8_t *)1, 0x00); | ||
| 97 | #endif | ||
| 98 | |||
| 92 | // watchdog reset | 99 | // watchdog reset |
| 93 | reset_key = BOOTLOADER_RESET_KEY; | 100 | reset_key = BOOTLOADER_RESET_KEY; |
| 94 | wdt_enable(WDTO_250MS); | 101 | wdt_enable(WDTO_250MS); |
| @@ -114,6 +121,11 @@ void bootloader_jump(void) { | |||
| 114 | #endif | 121 | #endif |
| 115 | } | 122 | } |
| 116 | 123 | ||
| 124 | #ifdef __AVR_ATmega32A__ | ||
| 125 | // MCUSR is actually called MCUCSR in ATmega32A | ||
| 126 | #define MCUSR MCUCSR | ||
| 127 | #endif | ||
| 128 | |||
| 117 | /* this runs before main() */ | 129 | /* this runs before main() */ |
| 118 | void bootloader_jump_after_watchdog_reset(void) __attribute__ ((used, naked, section (".init3"))); | 130 | void bootloader_jump_after_watchdog_reset(void) __attribute__ ((used, naked, section (".init3"))); |
| 119 | void bootloader_jump_after_watchdog_reset(void) | 131 | void bootloader_jump_after_watchdog_reset(void) |
diff --git a/tmk_core/common/avr/timer.c b/tmk_core/common/avr/timer.c index 84af44488..369015200 100644 --- a/tmk_core/common/avr/timer.c +++ b/tmk_core/common/avr/timer.c | |||
| @@ -29,25 +29,35 @@ volatile uint32_t timer_count; | |||
| 29 | 29 | ||
| 30 | void timer_init(void) | 30 | void timer_init(void) |
| 31 | { | 31 | { |
| 32 | // Timer0 CTC mode | ||
| 33 | TCCR0A = 0x02; | ||
| 34 | |||
| 35 | #if TIMER_PRESCALER == 1 | 32 | #if TIMER_PRESCALER == 1 |
| 36 | TCCR0B = 0x01; | 33 | uint8_t prescaler = 0x01; |
| 37 | #elif TIMER_PRESCALER == 8 | 34 | #elif TIMER_PRESCALER == 8 |
| 38 | TCCR0B = 0x02; | 35 | uint8_t prescaler = 0x02; |
| 39 | #elif TIMER_PRESCALER == 64 | 36 | #elif TIMER_PRESCALER == 64 |
| 40 | TCCR0B = 0x03; | 37 | uint8_t prescaler = 0x03; |
| 41 | #elif TIMER_PRESCALER == 256 | 38 | #elif TIMER_PRESCALER == 256 |
| 42 | TCCR0B = 0x04; | 39 | uint8_t prescaler = 0x04; |
| 43 | #elif TIMER_PRESCALER == 1024 | 40 | #elif TIMER_PRESCALER == 1024 |
| 44 | TCCR0B = 0x05; | 41 | uint8_t prescaler = 0x05; |
| 45 | #else | 42 | #else |
| 46 | # error "Timer prescaler value is NOT vaild." | 43 | # error "Timer prescaler value is NOT vaild." |
| 47 | #endif | 44 | #endif |
| 48 | 45 | ||
| 46 | #ifndef __AVR_ATmega32A__ | ||
| 47 | // Timer0 CTC mode | ||
| 48 | TCCR0A = 0x02; | ||
| 49 | |||
| 50 | TCCR0B = prescaler; | ||
| 51 | |||
| 49 | OCR0A = TIMER_RAW_TOP; | 52 | OCR0A = TIMER_RAW_TOP; |
| 50 | TIMSK0 = (1<<OCIE0A); | 53 | TIMSK0 = (1<<OCIE0A); |
| 54 | #else | ||
| 55 | // Timer0 CTC mode | ||
| 56 | TCCR0 = (1 << WGM01) | prescaler; | ||
| 57 | |||
| 58 | OCR0 = TIMER_RAW_TOP; | ||
| 59 | TIMSK = (1 << OCIE0); | ||
| 60 | #endif | ||
| 51 | } | 61 | } |
| 52 | 62 | ||
| 53 | inline | 63 | inline |
| @@ -107,7 +117,12 @@ uint32_t timer_elapsed32(uint32_t last) | |||
| 107 | } | 117 | } |
| 108 | 118 | ||
| 109 | // excecuted once per 1ms.(excess for just timer count?) | 119 | // excecuted once per 1ms.(excess for just timer count?) |
| 110 | ISR(TIMER0_COMPA_vect) | 120 | #ifndef __AVR_ATmega32A__ |
| 121 | #define TIMER_INTERRUPT_VECTOR TIMER0_COMPA_vect | ||
| 122 | #else | ||
| 123 | #define TIMER_INTERRUPT_VECTOR TIMER0_COMP_vect | ||
| 124 | #endif | ||
| 125 | ISR(TIMER_INTERRUPT_VECTOR, ISR_NOBLOCK) | ||
| 111 | { | 126 | { |
| 112 | timer_count++; | 127 | timer_count++; |
| 113 | } | 128 | } |
