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authorTakeshi ISHII <2170248+mtei@users.noreply.github.com>2021-08-24 22:34:24 +0900
committerGitHub <noreply@github.com>2021-08-24 14:34:24 +0100
commitc9c60d227e38abdf08ca86bcdad3a0cac2579e3f (patch)
tree03ec990a4d98c4a94330e4cccaadc76bc7381c67 /tmk_core/common/avr
parentc4dbf4bf0118dd785802861beb247433b5b7411d (diff)
downloadqmk_firmware-c9c60d227e38abdf08ca86bcdad3a0cac2579e3f.tar.gz
qmk_firmware-c9c60d227e38abdf08ca86bcdad3a0cac2579e3f.zip
add wait_cpuclock() macro for AVR and CPU_CLOCK macro (#12755)
Diffstat (limited to 'tmk_core/common/avr')
-rw-r--r--tmk_core/common/avr/_wait.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/tmk_core/common/avr/_wait.h b/tmk_core/common/avr/_wait.h
index ae1a25131..683db6ae5 100644
--- a/tmk_core/common/avr/_wait.h
+++ b/tmk_core/common/avr/_wait.h
@@ -37,6 +37,8 @@
37 } \ 37 } \
38 } \ 38 } \
39 } while (0) 39 } while (0)
40#define wait_cpuclock(n) __builtin_avr_delay_cycles(n)
41#define CPU_CLOCK F_CPU
40 42
41/* The AVR series GPIOs have a one clock read delay for changes in the digital input signal. 43/* The AVR series GPIOs have a one clock read delay for changes in the digital input signal.
42 * But here's more margin to make it two clocks. */ 44 * But here's more margin to make it two clocks. */
@@ -44,4 +46,4 @@
44# define GPIO_INPUT_PIN_DELAY 2 46# define GPIO_INPUT_PIN_DELAY 2
45#endif 47#endif
46 48
47#define waitInputPinDelay() __builtin_avr_delay_cycles(GPIO_INPUT_PIN_DELAY) 49#define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)