diff options
Diffstat (limited to 'drivers/sensors/adns9800.c')
| -rw-r--r-- | drivers/sensors/adns9800.c | 119 |
1 files changed, 55 insertions, 64 deletions
diff --git a/drivers/sensors/adns9800.c b/drivers/sensors/adns9800.c index 17966b81f..b4f683452 100644 --- a/drivers/sensors/adns9800.c +++ b/drivers/sensors/adns9800.c | |||
| @@ -20,57 +20,57 @@ | |||
| 20 | #include "adns9800.h" | 20 | #include "adns9800.h" |
| 21 | 21 | ||
| 22 | // registers | 22 | // registers |
| 23 | #define REG_Product_ID 0x00 | 23 | #define REG_Product_ID 0x00 |
| 24 | #define REG_Revision_ID 0x01 | 24 | #define REG_Revision_ID 0x01 |
| 25 | #define REG_Motion 0x02 | 25 | #define REG_Motion 0x02 |
| 26 | #define REG_Delta_X_L 0x03 | 26 | #define REG_Delta_X_L 0x03 |
| 27 | #define REG_Delta_X_H 0x04 | 27 | #define REG_Delta_X_H 0x04 |
| 28 | #define REG_Delta_Y_L 0x05 | 28 | #define REG_Delta_Y_L 0x05 |
| 29 | #define REG_Delta_Y_H 0x06 | 29 | #define REG_Delta_Y_H 0x06 |
| 30 | #define REG_SQUAL 0x07 | 30 | #define REG_SQUAL 0x07 |
| 31 | #define REG_Pixel_Sum 0x08 | 31 | #define REG_Pixel_Sum 0x08 |
| 32 | #define REG_Maximum_Pixel 0x09 | 32 | #define REG_Maximum_Pixel 0x09 |
| 33 | #define REG_Minimum_Pixel 0x0a | 33 | #define REG_Minimum_Pixel 0x0a |
| 34 | #define REG_Shutter_Lower 0x0b | 34 | #define REG_Shutter_Lower 0x0b |
| 35 | #define REG_Shutter_Upper 0x0c | 35 | #define REG_Shutter_Upper 0x0c |
| 36 | #define REG_Frame_Period_Lower 0x0d | 36 | #define REG_Frame_Period_Lower 0x0d |
| 37 | #define REG_Frame_Period_Upper 0x0e | 37 | #define REG_Frame_Period_Upper 0x0e |
| 38 | #define REG_Configuration_I 0x0f | 38 | #define REG_Configuration_I 0x0f |
| 39 | #define REG_Configuration_II 0x10 | 39 | #define REG_Configuration_II 0x10 |
| 40 | #define REG_Frame_Capture 0x12 | 40 | #define REG_Frame_Capture 0x12 |
| 41 | #define REG_SROM_Enable 0x13 | 41 | #define REG_SROM_Enable 0x13 |
| 42 | #define REG_Run_Downshift 0x14 | 42 | #define REG_Run_Downshift 0x14 |
| 43 | #define REG_Rest1_Rate 0x15 | 43 | #define REG_Rest1_Rate 0x15 |
| 44 | #define REG_Rest1_Downshift 0x16 | 44 | #define REG_Rest1_Downshift 0x16 |
| 45 | #define REG_Rest2_Rate 0x17 | 45 | #define REG_Rest2_Rate 0x17 |
| 46 | #define REG_Rest2_Downshift 0x18 | 46 | #define REG_Rest2_Downshift 0x18 |
| 47 | #define REG_Rest3_Rate 0x19 | 47 | #define REG_Rest3_Rate 0x19 |
| 48 | #define REG_Frame_Period_Max_Bound_Lower 0x1a | 48 | #define REG_Frame_Period_Max_Bound_Lower 0x1a |
| 49 | #define REG_Frame_Period_Max_Bound_Upper 0x1b | 49 | #define REG_Frame_Period_Max_Bound_Upper 0x1b |
| 50 | #define REG_Frame_Period_Min_Bound_Lower 0x1c | 50 | #define REG_Frame_Period_Min_Bound_Lower 0x1c |
| 51 | #define REG_Frame_Period_Min_Bound_Upper 0x1d | 51 | #define REG_Frame_Period_Min_Bound_Upper 0x1d |
| 52 | #define REG_Shutter_Max_Bound_Lower 0x1e | 52 | #define REG_Shutter_Max_Bound_Lower 0x1e |
| 53 | #define REG_Shutter_Max_Bound_Upper 0x1f | 53 | #define REG_Shutter_Max_Bound_Upper 0x1f |
| 54 | #define REG_LASER_CTRL0 0x20 | 54 | #define REG_LASER_CTRL0 0x20 |
| 55 | #define REG_Observation 0x24 | 55 | #define REG_Observation 0x24 |
| 56 | #define REG_Data_Out_Lower 0x25 | 56 | #define REG_Data_Out_Lower 0x25 |
| 57 | #define REG_Data_Out_Upper 0x26 | 57 | #define REG_Data_Out_Upper 0x26 |
| 58 | #define REG_SROM_ID 0x2a | 58 | #define REG_SROM_ID 0x2a |
| 59 | #define REG_Lift_Detection_Thr 0x2e | 59 | #define REG_Lift_Detection_Thr 0x2e |
| 60 | #define REG_Configuration_V 0x2f | 60 | #define REG_Configuration_V 0x2f |
| 61 | #define REG_Configuration_IV 0x39 | 61 | #define REG_Configuration_IV 0x39 |
| 62 | #define REG_Power_Up_Reset 0x3a | 62 | #define REG_Power_Up_Reset 0x3a |
| 63 | #define REG_Shutdown 0x3b | 63 | #define REG_Shutdown 0x3b |
| 64 | #define REG_Inverse_Product_ID 0x3f | 64 | #define REG_Inverse_Product_ID 0x3f |
| 65 | #define REG_Motion_Burst 0x50 | 65 | #define REG_Motion_Burst 0x50 |
| 66 | #define REG_SROM_Load_Burst 0x62 | 66 | #define REG_SROM_Load_Burst 0x62 |
| 67 | #define REG_Pixel_Burst 0x64 | 67 | #define REG_Pixel_Burst 0x64 |
| 68 | 68 | ||
| 69 | #define ADNS_CLOCK_SPEED 2000000 | 69 | #define ADNS_CLOCK_SPEED 2000000 |
| 70 | #define MIN_CPI 200 | 70 | #define MIN_CPI 200 |
| 71 | #define MAX_CPI 8200 | 71 | #define MAX_CPI 8200 |
| 72 | #define CPI_STEP 200 | 72 | #define CPI_STEP 200 |
| 73 | #define CLAMP_CPI(value) value < MIN_CPI ? MIN_CPI : value > MAX_CPI ? MAX_CPI : value | 73 | #define CLAMP_CPI(value) value<MIN_CPI ? MIN_CPI : value> MAX_CPI ? MAX_CPI : value |
| 74 | #define SPI_MODE 3 | 74 | #define SPI_MODE 3 |
| 75 | #define SPI_DIVISOR (F_CPU / ADNS_CLOCK_SPEED) | 75 | #define SPI_DIVISOR (F_CPU / ADNS_CLOCK_SPEED) |
| 76 | #define US_BETWEEN_WRITES 120 | 76 | #define US_BETWEEN_WRITES 120 |
| @@ -80,12 +80,9 @@ | |||
| 80 | 80 | ||
| 81 | extern const uint8_t firmware_data[]; | 81 | extern const uint8_t firmware_data[]; |
| 82 | 82 | ||
| 83 | void adns_spi_start(void){ | 83 | void adns_spi_start(void) { spi_start(SPI_SS_PIN, false, SPI_MODE, SPI_DIVISOR); } |
| 84 | spi_start(SPI_SS_PIN, false, SPI_MODE, SPI_DIVISOR); | ||
| 85 | } | ||
| 86 | |||
| 87 | void adns_write(uint8_t reg_addr, uint8_t data){ | ||
| 88 | 84 | ||
| 85 | void adns_write(uint8_t reg_addr, uint8_t data) { | ||
| 89 | adns_spi_start(); | 86 | adns_spi_start(); |
| 90 | spi_write(reg_addr | MSB1); | 87 | spi_write(reg_addr | MSB1); |
| 91 | spi_write(data); | 88 | spi_write(data); |
| @@ -93,10 +90,9 @@ void adns_write(uint8_t reg_addr, uint8_t data){ | |||
| 93 | wait_us(US_BETWEEN_WRITES); | 90 | wait_us(US_BETWEEN_WRITES); |
| 94 | } | 91 | } |
| 95 | 92 | ||
| 96 | uint8_t adns_read(uint8_t reg_addr){ | 93 | uint8_t adns_read(uint8_t reg_addr) { |
| 97 | |||
| 98 | adns_spi_start(); | 94 | adns_spi_start(); |
| 99 | spi_write(reg_addr & 0x7f ); | 95 | spi_write(reg_addr & 0x7f); |
| 100 | uint8_t data = spi_read(); | 96 | uint8_t data = spi_read(); |
| 101 | spi_stop(); | 97 | spi_stop(); |
| 102 | wait_us(US_BETWEEN_READS); | 98 | wait_us(US_BETWEEN_READS); |
| @@ -105,7 +101,6 @@ uint8_t adns_read(uint8_t reg_addr){ | |||
| 105 | } | 101 | } |
| 106 | 102 | ||
| 107 | void adns_init() { | 103 | void adns_init() { |
| 108 | |||
| 109 | setPinOutput(SPI_SS_PIN); | 104 | setPinOutput(SPI_SS_PIN); |
| 110 | 105 | ||
| 111 | spi_init(); | 106 | spi_init(); |
| @@ -144,7 +139,7 @@ void adns_init() { | |||
| 144 | 139 | ||
| 145 | // send all bytes of the firmware | 140 | // send all bytes of the firmware |
| 146 | unsigned char c; | 141 | unsigned char c; |
| 147 | for(int i = 0; i < FIRMWARE_LENGTH; i++){ | 142 | for (int i = 0; i < FIRMWARE_LENGTH; i++) { |
| 148 | c = (unsigned char)pgm_read_byte(firmware_data + i); | 143 | c = (unsigned char)pgm_read_byte(firmware_data + i); |
| 149 | spi_write(c); | 144 | spi_write(c); |
| 150 | wait_us(15); | 145 | wait_us(15); |
| @@ -161,7 +156,7 @@ void adns_init() { | |||
| 161 | 156 | ||
| 162 | config_adns_t adns_get_config(void) { | 157 | config_adns_t adns_get_config(void) { |
| 163 | uint8_t config_1 = adns_read(REG_Configuration_I); | 158 | uint8_t config_1 = adns_read(REG_Configuration_I); |
| 164 | return (config_adns_t){ (config_1 & 0xFF) * CPI_STEP }; | 159 | return (config_adns_t){(config_1 & 0xFF) * CPI_STEP}; |
| 165 | } | 160 | } |
| 166 | 161 | ||
| 167 | void adns_set_config(config_adns_t config) { | 162 | void adns_set_config(config_adns_t config) { |
| @@ -169,20 +164,17 @@ void adns_set_config(config_adns_t config) { | |||
| 169 | adns_write(REG_Configuration_I, config_1); | 164 | adns_write(REG_Configuration_I, config_1); |
| 170 | } | 165 | } |
| 171 | 166 | ||
| 172 | static int16_t convertDeltaToInt(uint8_t high, uint8_t low){ | 167 | static int16_t convertDeltaToInt(uint8_t high, uint8_t low) { |
| 173 | |||
| 174 | // join bytes into twos compliment | 168 | // join bytes into twos compliment |
| 175 | uint16_t twos_comp = (high << 8) | low; | 169 | uint16_t twos_comp = (high << 8) | low; |
| 176 | 170 | ||
| 177 | // convert twos comp to int | 171 | // convert twos comp to int |
| 178 | if (twos_comp & 0x8000) | 172 | if (twos_comp & 0x8000) return -1 * (~twos_comp + 1); |
| 179 | return -1 * (~twos_comp + 1); | ||
| 180 | 173 | ||
| 181 | return twos_comp; | 174 | return twos_comp; |
| 182 | } | 175 | } |
| 183 | 176 | ||
| 184 | report_adns_t adns_get_report(void) { | 177 | report_adns_t adns_get_report(void) { |
| 185 | |||
| 186 | report_adns_t report = {0, 0}; | 178 | report_adns_t report = {0, 0}; |
| 187 | 179 | ||
| 188 | adns_spi_start(); | 180 | adns_spi_start(); |
| @@ -194,8 +186,7 @@ report_adns_t adns_get_report(void) { | |||
| 194 | 186 | ||
| 195 | uint8_t motion = spi_read(); | 187 | uint8_t motion = spi_read(); |
| 196 | 188 | ||
| 197 | if(motion & 0x80) { | 189 | if (motion & 0x80) { |
| 198 | |||
| 199 | // clear observation register | 190 | // clear observation register |
| 200 | spi_read(); | 191 | spi_read(); |
| 201 | 192 | ||
