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Diffstat (limited to 'keyboards/dc01/left/i2c.c')
-rw-r--r-- | keyboards/dc01/left/i2c.c | 159 |
1 files changed, 159 insertions, 0 deletions
diff --git a/keyboards/dc01/left/i2c.c b/keyboards/dc01/left/i2c.c new file mode 100644 index 000000000..c72789403 --- /dev/null +++ b/keyboards/dc01/left/i2c.c | |||
@@ -0,0 +1,159 @@ | |||
1 | #include <util/twi.h> | ||
2 | #include <avr/io.h> | ||
3 | #include <stdlib.h> | ||
4 | #include <avr/interrupt.h> | ||
5 | #include <util/twi.h> | ||
6 | #include <stdbool.h> | ||
7 | #include "i2c.h" | ||
8 | |||
9 | // Limits the amount of we wait for any one i2c transaction. | ||
10 | // Since were running SCL line 100kHz (=> 10μs/bit), and each transactions is | ||
11 | // 9 bits, a single transaction will take around 90μs to complete. | ||
12 | // | ||
13 | // (F_CPU/SCL_CLOCK) => # of μC cycles to transfer a bit | ||
14 | // poll loop takes at least 8 clock cycles to execute | ||
15 | #define I2C_LOOP_TIMEOUT (9+1)*(F_CPU/SCL_CLOCK)/8 | ||
16 | |||
17 | #define BUFFER_POS_INC() (slave_buffer_pos = (slave_buffer_pos+1)%SLAVE_BUFFER_SIZE) | ||
18 | |||
19 | volatile uint8_t i2c_slave_buffer[SLAVE_BUFFER_SIZE]; | ||
20 | |||
21 | static volatile uint8_t slave_buffer_pos; | ||
22 | static volatile bool slave_has_register_set = false; | ||
23 | |||
24 | // Wait for an i2c operation to finish | ||
25 | inline static | ||
26 | void i2c_delay(void) { | ||
27 | uint16_t lim = 0; | ||
28 | while(!(TWCR & (1<<TWINT)) && lim < I2C_LOOP_TIMEOUT) | ||
29 | lim++; | ||
30 | |||
31 | // easier way, but will wait slightly longer | ||
32 | // _delay_us(100); | ||
33 | } | ||
34 | |||
35 | // Setup twi to run at 100kHz | ||
36 | void i2c_master_init(void) { | ||
37 | // no prescaler | ||
38 | TWSR = 0; | ||
39 | // Set TWI clock frequency to SCL_CLOCK. Need TWBR>10. | ||
40 | // Check datasheets for more info. | ||
41 | TWBR = ((F_CPU/SCL_CLOCK)-16)/2; | ||
42 | } | ||
43 | |||
44 | // Start a transaction with the given i2c slave address. The direction of the | ||
45 | // transfer is set with I2C_READ and I2C_WRITE. | ||
46 | // returns: 0 => success | ||
47 | // 1 => error | ||
48 | uint8_t i2c_master_start(uint8_t address) { | ||
49 | TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTA); | ||
50 | |||
51 | i2c_delay(); | ||
52 | |||
53 | // check that we started successfully | ||
54 | if ( (TW_STATUS != TW_START) && (TW_STATUS != TW_REP_START)) | ||
55 | return 1; | ||
56 | |||
57 | TWDR = address; | ||
58 | TWCR = (1<<TWINT) | (1<<TWEN); | ||
59 | |||
60 | i2c_delay(); | ||
61 | |||
62 | if ( (TW_STATUS != TW_MT_SLA_ACK) && (TW_STATUS != TW_MR_SLA_ACK) ) | ||
63 | return 1; // slave did not acknowledge | ||
64 | else | ||
65 | return 0; // success | ||
66 | } | ||
67 | |||
68 | |||
69 | // Finish the i2c transaction. | ||
70 | void i2c_master_stop(void) { | ||
71 | TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO); | ||
72 | |||
73 | uint16_t lim = 0; | ||
74 | while(!(TWCR & (1<<TWSTO)) && lim < I2C_LOOP_TIMEOUT) | ||
75 | lim++; | ||
76 | } | ||
77 | |||
78 | // Write one byte to the i2c slave. | ||
79 | // returns 0 => slave ACK | ||
80 | // 1 => slave NACK | ||
81 | uint8_t i2c_master_write(uint8_t data) { | ||
82 | TWDR = data; | ||
83 | TWCR = (1<<TWINT) | (1<<TWEN); | ||
84 | |||
85 | i2c_delay(); | ||
86 | |||
87 | // check if the slave acknowledged us | ||
88 | return (TW_STATUS == TW_MT_DATA_ACK) ? 0 : 1; | ||
89 | } | ||
90 | |||
91 | // Read one byte from the i2c slave. If ack=1 the slave is acknowledged, | ||
92 | // if ack=0 the acknowledge bit is not set. | ||
93 | // returns: byte read from i2c device | ||
94 | uint8_t i2c_master_read(int ack) { | ||
95 | TWCR = (1<<TWINT) | (1<<TWEN) | (ack<<TWEA); | ||
96 | |||
97 | i2c_delay(); | ||
98 | return TWDR; | ||
99 | } | ||
100 | |||
101 | void i2c_reset_state(void) { | ||
102 | TWCR = 0; | ||
103 | } | ||
104 | |||
105 | void i2c_slave_init(uint8_t address) { | ||
106 | TWAR = address << 0; // slave i2c address | ||
107 | // TWEN - twi enable | ||
108 | // TWEA - enable address acknowledgement | ||
109 | // TWINT - twi interrupt flag | ||
110 | // TWIE - enable the twi interrupt | ||
111 | TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN); | ||
112 | } | ||
113 | |||
114 | ISR(TWI_vect); | ||
115 | |||
116 | ISR(TWI_vect) { | ||
117 | uint8_t ack = 1; | ||
118 | switch(TW_STATUS) { | ||
119 | case TW_SR_SLA_ACK: | ||
120 | // this device has been addressed as a slave receiver | ||
121 | slave_has_register_set = false; | ||
122 | break; | ||
123 | |||
124 | case TW_SR_DATA_ACK: | ||
125 | // this device has received data as a slave receiver | ||
126 | // The first byte that we receive in this transaction sets the location | ||
127 | // of the read/write location of the slaves memory that it exposes over | ||
128 | // i2c. After that, bytes will be written at slave_buffer_pos, incrementing | ||
129 | // slave_buffer_pos after each write. | ||
130 | if(!slave_has_register_set) { | ||
131 | slave_buffer_pos = TWDR; | ||
132 | // don't acknowledge the master if this memory loctaion is out of bounds | ||
133 | if ( slave_buffer_pos >= SLAVE_BUFFER_SIZE ) { | ||
134 | ack = 0; | ||
135 | slave_buffer_pos = 0; | ||
136 | } | ||
137 | slave_has_register_set = true; | ||
138 | } else { | ||
139 | i2c_slave_buffer[slave_buffer_pos] = TWDR; | ||
140 | BUFFER_POS_INC(); | ||
141 | } | ||
142 | break; | ||
143 | |||
144 | case TW_ST_SLA_ACK: | ||
145 | case TW_ST_DATA_ACK: | ||
146 | // master has addressed this device as a slave transmitter and is | ||
147 | // requesting data. | ||
148 | TWDR = i2c_slave_buffer[slave_buffer_pos]; | ||
149 | BUFFER_POS_INC(); | ||
150 | break; | ||
151 | |||
152 | case TW_BUS_ERROR: // something went wrong, reset twi state | ||
153 | TWCR = 0; | ||
154 | default: | ||
155 | break; | ||
156 | } | ||
157 | // Reset everything, so we are ready for the next TWI interrupt | ||
158 | TWCR |= (1<<TWIE) | (1<<TWINT) | (ack<<TWEA) | (1<<TWEN); | ||
159 | } | ||