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1/* Copyright (C) 2015 Andrew J. Kroll
2 and
3 Circuits At Home, LTD. All rights reserved.
4
5This software may be distributed and modified under the terms of the GNU
6General Public License version 2 (GPL2) as published by the Free Software
7Foundation and appearing in the file GPL2.TXT included in the packaging of
8this file. Please note that GPL2 Section 2[b] requires that all works based
9on this software must also be made publicly available under the terms of
10the GPL2 ("Copyleft").
11
12Contact information
13-------------------
14
15Circuits At Home, LTD
16Web : http://www.circuitsathome.com
17e-mail : support@circuitsathome.com
18 */
19#if !defined(__CDC_XR21B1411_H__)
20#define __CDC_XR21B1411_H__
21
22#include "cdcacm.h"
23
24#define XR_REG_CUSTOM_DRIVER (0x020DU) // DRIVER SELECT
25#define XR_REG_CUSTOM_DRIVER_ACTIVE (0x0001U) // 0: CDC 1: CUSTOM
26
27#define XR_REG_ACM_FLOW_CTL (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE
28#define XR_REG_FLOW_CTL (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE
29#define XR_REG_FLOW_CTL_HALF_DPLX (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX
30#define XR_REG_FLOW_CTL_MODE_MASK (0x0007U) // MODE BITMASK
31#define XR_REG_FLOW_CTL_NONE (0x0000U) // NO FLOW CONTROL
32#define XR_REG_FLOW_CTL_HW (0x0001U) // HARDWARE FLOW CONTROL
33#define XR_REG_FLOW_CTL_SW (0x0002U) // SOFTWARE FLOW CONTROL
34#define XR_REG_FLOW_CTL_MMMRX (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH
35#define XR_REG_FLOW_CTL_MMMRXTX (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH
36
37#define XR_REG_ACM_GPIO_MODE (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE
38#define XR_REG_GPIO_MODE (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE
39#define XR_REG_GPIO_MODE_GPIO (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE
40#define XR_REG_GPIO_MODE_FC_RTSCTS (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5)
41#define XR_REG_GPIO_MODE_FC_DTRDSR (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3)
42#define XR_REG_GPIO_MODE_ATE (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5)
43#define XR_REG_GPIO_MODE_ATE_ADDRESS (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5)
44
45#define XR_REG_ACM_GPIO_DIR (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT
46#define XR_REG_GPIO_DIR (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT
47
48#define XR_REG_ACM_GPIO_INT (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED
49#define XR_REG_GPIO_INT (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED
50#define XR_REG_GPIO_MASK (0x001FU) // GPIO REGISTERS BITMASK
51
52#define XR_REG_UART_ENABLE (0x0C00U) // UART I/O ENABLE REGISTER
53#define XR_REG_UART_ENABLE_RX (0x0002U) // 0:DISABLED 1:ENABLED
54#define XR_REG_UART_ENABLE_TX (0x0001U) // 0:DISABLED 1:ENABLED
55
56#define XR_REG_ERROR_STATUS (0x0C09U) // ERROR STATUS REGISTER
57#define XR_REG_ERROR_STATUS_MASK (0x00F8U) // ERROR STATUS BITMASK
58#define XR_REG_ERROR_STATUS_ERROR (0x0078U) // ERROR STATUS ERROR BITMASK
59#define XR_REG_ERROR_STATUS_BREAK (0x0008U) // BREAK ERROR HAS BEEN DETECTED
60#define XR_REG_ERROR_STATUS_FRAME (0x0010U) // FRAMING ERROR HAS BEEN DETECTED
61#define XR_REG_ERROR_STATUS_PARITY (0x0020U) // PARITY ERROR HAS BEEN DETECTED
62#define XR_REG_ERROR_STATUS_OVERRUN (0x0040U) // RX OVERRUN ERROR HAS BEEN DETECTED
63#define XR_REG_ERROR_STATUS_BREAK_STATUS (0x0080U) // BREAK CONDITION IS CURRENTLY BEING DETECTED
64
65#define XR_REG_TX_BREAK (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON
66
67#define XR_REG_XCVR_EN_DELAY (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F
68
69#define XR_REG_GPIO_SET (0x0C0EU) // 1:SET GPIO PIN
70
71#define XR_REG_GPIO_CLR (0x0C0FU) // 1:CLEAR GPIO PIN
72
73#define XR_REG_GPIO_STATUS (0x0C10U) // READ GPIO PINS
74
75#define XR_REG_CUSTOMISED_INT (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET
76
77#define XR_REG_PIN_PULLUP_ENABLE (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
78
79#define XR_REG_PIN_PULLDOWN_ENABLE (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
80
81#define XR_REG_LOOPBACK (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET
82
83#define XR_REG_RX_FIFO_LATENCY (0x0CC2U) // FIFO LATENCY REGISTER
84#define XR_REG_RX_FIFO_LATENCY_ENABLE (0x0001U) //
85
86#define XR_REG_WIDE_MODE (0x0D02U)
87#define XR_REG_WIDE_MODE_ENABLE (0x0001U)
88
89#define XR_REG_XON_CHAR (0x0C07U)
90#define XR_REG_XOFF_CHAR (0x0C08U)
91
92#define XR_REG_TX_FIFO_RESET (0x0C80U) // 1: RESET, SELF-CLEARING
93#define XR_REG_TX_FIFO_COUNT (0x0C81U) // READ-ONLY
94#define XR_REG_RX_FIFO_RESET (0x0CC0U) // 1: RESET, SELF-CLEARING
95#define XR_REG_RX_FIFO_COUNT (0x0CC1U) // READ-ONLY
96
97#define XR_WRITE_REQUEST_TYPE (0x40U)
98
99#define XR_READ_REQUEST_TYPE (0xC0U)
100
101#define XR_MAX_ENDPOINTS 4
102
103class XR21B1411 : public ACM {
104protected:
105
106public:
107 XR21B1411(USB *pusb, CDCAsyncOper *pasync);
108
109 /**
110 * Used by the USB core to check what this driver support.
111 * @param vid The device's VID.
112 * @param pid The device's PID.
113 * @return Returns true if the device's VID and PID matches this driver.
114 */
115 virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
116 return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
117 };
118
119 uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
120
121 virtual tty_features enhanced_features(void) {
122 tty_features rv;
123 rv.enhanced = true;
124 rv.autoflow_RTS = true;
125 rv.autoflow_DSR = true;
126 rv.autoflow_XON = true;
127 rv.half_duplex = true;
128 rv.wide = true;
129 return rv;
130 };
131
132 uint8_t read_register(uint16_t reg, uint16_t *val) {
133 return (pUsb->ctrlReq(bAddress, 0, XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
134 }
135
136 uint8_t write_register(uint16_t reg, uint16_t val) {
137 return (pUsb->ctrlReq(bAddress, 0, XR_WRITE_REQUEST_TYPE, 0, BGRAB0(val), BGRAB1(val), reg, 0, 0, NULL, NULL));
138 }
139
140
141 ////////////////////////////////////////////////////////////////////////
142 // The following methods set the CDC-ACM defaults.
143 ////////////////////////////////////////////////////////////////////////
144
145 virtual void autoflowRTS(bool s) {
146 uint16_t val;
147 uint8_t rval;
148 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
149 if(!rval) {
150 if(s) {
151 val &= XR_REG_FLOW_CTL_HALF_DPLX;
152 val |= XR_REG_FLOW_CTL_HW;
153 } else {
154 val &= XR_REG_FLOW_CTL_HALF_DPLX;
155 }
156 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
157 if(!rval) {
158 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
159 if(!rval) {
160 // ACM commands apply the new settings.
161 LINE_CODING LCT;
162 rval = GetLineCoding(&LCT);
163 if(!rval) {
164 rval = SetLineCoding(&LCT);
165 if(!rval) {
166 _enhanced_status.autoflow_XON = false;
167 _enhanced_status.autoflow_DSR = false;
168 _enhanced_status.autoflow_RTS = s;
169 }
170 }
171 }
172 }
173 }
174 };
175
176 virtual void autoflowDSR(bool s) {
177 uint16_t val;
178 uint8_t rval;
179 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
180 if(!rval) {
181 if(s) {
182 val &= XR_REG_FLOW_CTL_HALF_DPLX;
183 val |= XR_REG_FLOW_CTL_HW;
184 } else {
185 val &= XR_REG_FLOW_CTL_HALF_DPLX;
186 }
187 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
188 if(!rval) {
189 if(s) {
190 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_FC_DTRDSR);
191 } else {
192 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
193 }
194 if(!rval) {
195 // ACM commands apply the new settings.
196 LINE_CODING LCT;
197 rval = GetLineCoding(&LCT);
198 if(!rval) {
199 rval = SetLineCoding(&LCT);
200 if(!rval) {
201 _enhanced_status.autoflow_XON = false;
202 _enhanced_status.autoflow_RTS = false;
203 _enhanced_status.autoflow_DSR = s;
204 }
205 }
206 }
207 }
208 }
209 };
210
211 virtual void autoflowXON(bool s) {
212 // NOTE: hardware defaults to the normal XON/XOFF
213 uint16_t val;
214 uint8_t rval;
215 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
216 if(!rval) {
217 if(s) {
218 val &= XR_REG_FLOW_CTL_HALF_DPLX;
219 val |= XR_REG_FLOW_CTL_SW;
220 } else {
221 val &= XR_REG_FLOW_CTL_HALF_DPLX;
222 }
223 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
224 if(!rval) {
225 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
226 if(!rval) {
227 // ACM commands apply the new settings.
228 LINE_CODING LCT;
229 rval = GetLineCoding(&LCT);
230 if(!rval) {
231 rval = SetLineCoding(&LCT);
232 if(!rval) {
233 _enhanced_status.autoflow_RTS = false;
234 _enhanced_status.autoflow_DSR = false;
235 _enhanced_status.autoflow_XON = s;
236 }
237 }
238 }
239 }
240 }
241 };
242
243 virtual void half_duplex(bool s) {
244 uint16_t val;
245 uint8_t rval;
246 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
247 if(!rval) {
248 if(s) {
249 val |= XR_REG_FLOW_CTL_HALF_DPLX;
250 } else {
251 val &= XR_REG_FLOW_CTL_MODE_MASK;
252 }
253 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
254 if(!rval) {
255 // ACM commands apply the new settings.
256 LINE_CODING LCT;
257 rval = GetLineCoding(&LCT);
258 if(!rval) {
259 rval = SetLineCoding(&LCT);
260 if(!rval) {
261 _enhanced_status.half_duplex = s;
262 }
263 }
264 }
265 }
266 };
267
268
269
270};
271
272#endif // __CDCPROLIFIC_H__
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