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-rw-r--r--platforms/chibios/GENERIC_STM32_G431XB/board/board.mk9
-rw-r--r--platforms/chibios/GENERIC_STM32_G431XB/configs/config.h23
-rw-r--r--platforms/chibios/GENERIC_STM32_G431XB/configs/mcuconf.h307
-rw-r--r--platforms/chibios/GENERIC_STM32_G474XE/board/board.mk9
-rw-r--r--platforms/chibios/GENERIC_STM32_G474XE/configs/config.h30
-rw-r--r--platforms/chibios/GENERIC_STM32_G474XE/configs/mcuconf.h372
6 files changed, 750 insertions, 0 deletions
diff --git a/platforms/chibios/GENERIC_STM32_G431XB/board/board.mk b/platforms/chibios/GENERIC_STM32_G431XB/board/board.mk
new file mode 100644
index 000000000..0acbcd83c
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G431XB/board/board.mk
@@ -0,0 +1,9 @@
1# List of all the board related files.
2BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB/board.c
3
4# Required include directories
5BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB
6
7# Shared variables
8ALLCSRC += $(BOARDSRC)
9ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/GENERIC_STM32_G431XB/configs/config.h b/platforms/chibios/GENERIC_STM32_G431XB/configs/config.h
new file mode 100644
index 000000000..39ce627e7
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G431XB/configs/config.h
@@ -0,0 +1,23 @@
1/* Copyright 2018-2020 Nick Brassel (@tzarc)
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Address for jumping to bootloader on STM32 chips. */
18/* It is chip dependent, the correct number can be looked up here (page 175):
19 * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
20 * This also requires a patch to chibios:
21 * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
22 */
23#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
diff --git a/platforms/chibios/GENERIC_STM32_G431XB/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_G431XB/configs/mcuconf.h
new file mode 100644
index 000000000..182d4885d
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G431XB/configs/mcuconf.h
@@ -0,0 +1,307 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * STM32G4xx drivers configuration.
19 * The following settings override the default settings present in
20 * the various device driver implementation headers.
21 * Note that the settings for each driver only have effect if the whole
22 * driver is enabled in halconf.h.
23 *
24 * IRQ priorities:
25 * 15...0 Lowest...Highest.
26 *
27 * DMA priorities:
28 * 0...3 Lowest...Highest.
29 */
30
31#ifndef MCUCONF_H
32#define MCUCONF_H
33
34#define STM32G4xx_MCUCONF
35#define STM32G431_MCUCONF
36#define STM32G441_MCUCONF
37
38/*
39 * HAL driver system settings.
40 */
41#define STM32_NO_INIT FALSE
42#define STM32_VOS STM32_VOS_RANGE1
43#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
44#define STM32_PWR_CR3 (PWR_CR3_EIWF)
45#define STM32_PWR_CR4 (0U)
46#define STM32_HSI16_ENABLED TRUE
47#define STM32_HSI48_ENABLED TRUE
48#define STM32_HSE_ENABLED FALSE
49#define STM32_LSI_ENABLED TRUE
50#define STM32_LSE_ENABLED FALSE
51#define STM32_SW STM32_SW_PLLRCLK
52#define STM32_PLLSRC STM32_PLLSRC_HSI16
53#define STM32_PLLM_VALUE 4
54#define STM32_PLLN_VALUE 80
55#define STM32_PLLPDIV_VALUE 0
56#define STM32_PLLP_VALUE 7
57#define STM32_PLLQ_VALUE 8
58#define STM32_PLLR_VALUE 2
59#define STM32_HPRE STM32_HPRE_DIV1
60#define STM32_PPRE1 STM32_PPRE1_DIV1
61#define STM32_PPRE2 STM32_PPRE2_DIV1
62#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
63#define STM32_MCOPRE STM32_MCOPRE_DIV1
64#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
65
66/*
67 * Peripherals clock sources.
68 */
69#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
70#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
71#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
72#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
73#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
74#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
75#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
76#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
77#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
78#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
79#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
80#define STM32_FDCANSEL STM32_FDCANSEL_PCLK1
81#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
82#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
83#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
84
85/*
86 * IRQ system settings.
87 */
88#define STM32_IRQ_EXTI0_PRIORITY 6
89#define STM32_IRQ_EXTI1_PRIORITY 6
90#define STM32_IRQ_EXTI2_PRIORITY 6
91#define STM32_IRQ_EXTI3_PRIORITY 6
92#define STM32_IRQ_EXTI4_PRIORITY 6
93#define STM32_IRQ_EXTI5_9_PRIORITY 6
94#define STM32_IRQ_EXTI10_15_PRIORITY 6
95#define STM32_IRQ_EXTI164041_PRIORITY 6
96#define STM32_IRQ_EXTI17_PRIORITY 6
97#define STM32_IRQ_EXTI18_PRIORITY 6
98#define STM32_IRQ_EXTI19_PRIORITY 6
99#define STM32_IRQ_EXTI20_PRIORITY 6
100#define STM32_IRQ_EXTI212229_PRIORITY 6
101#define STM32_IRQ_EXTI30_32_PRIORITY 6
102#define STM32_IRQ_EXTI33_PRIORITY 6
103
104#define STM32_IRQ_FDCAN1_PRIORITY 10
105
106#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
107#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
108#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
109#define STM32_IRQ_TIM1_CC_PRIORITY 7
110#define STM32_IRQ_TIM2_PRIORITY 7
111#define STM32_IRQ_TIM3_PRIORITY 7
112#define STM32_IRQ_TIM4_PRIORITY 7
113#define STM32_IRQ_TIM6_PRIORITY 7
114#define STM32_IRQ_TIM7_PRIORITY 7
115#define STM32_IRQ_TIM8_UP_PRIORITY 7
116#define STM32_IRQ_TIM8_CC_PRIORITY 7
117
118#define STM32_IRQ_USART1_PRIORITY 12
119#define STM32_IRQ_USART2_PRIORITY 12
120#define STM32_IRQ_USART3_PRIORITY 12
121#define STM32_IRQ_UART4_PRIORITY 12
122#define STM32_IRQ_LPUART1_PRIORITY 12
123
124/*
125 * ADC driver system settings.
126 */
127#define STM32_ADC_DUAL_MODE FALSE
128#define STM32_ADC_COMPACT_SAMPLES FALSE
129#define STM32_ADC_USE_ADC1 FALSE
130#define STM32_ADC_USE_ADC2 FALSE
131#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
132#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
133#define STM32_ADC_ADC1_DMA_PRIORITY 2
134#define STM32_ADC_ADC2_DMA_PRIORITY 2
135#define STM32_ADC_ADC12_IRQ_PRIORITY 5
136#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
137#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
138#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
139#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
140
141/*
142 * CAN driver system settings.
143 */
144#define STM32_CAN_USE_FDCAN1 FALSE
145
146/*
147 * DAC driver system settings.
148 */
149#define STM32_DAC_DUAL_MODE FALSE
150#define STM32_DAC_USE_DAC1_CH1 FALSE
151#define STM32_DAC_USE_DAC1_CH2 FALSE
152#define STM32_DAC_USE_DAC3_CH1 FALSE
153#define STM32_DAC_USE_DAC3_CH2 FALSE
154#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
155#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
156#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
157#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
158#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
159#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
160#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
161#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
162#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
163#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
164#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
165#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
166
167/*
168 * GPT driver system settings.
169 */
170#define STM32_GPT_USE_TIM1 FALSE
171#define STM32_GPT_USE_TIM2 FALSE
172#define STM32_GPT_USE_TIM3 FALSE
173#define STM32_GPT_USE_TIM4 FALSE
174#define STM32_GPT_USE_TIM6 FALSE
175#define STM32_GPT_USE_TIM7 FALSE
176#define STM32_GPT_USE_TIM8 FALSE
177#define STM32_GPT_USE_TIM15 FALSE
178#define STM32_GPT_USE_TIM16 FALSE
179#define STM32_GPT_USE_TIM17 FALSE
180
181/*
182 * I2C driver system settings.
183 */
184#define STM32_I2C_USE_I2C1 FALSE
185#define STM32_I2C_USE_I2C2 FALSE
186#define STM32_I2C_USE_I2C3 FALSE
187#define STM32_I2C_BUSY_TIMEOUT 50
188#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
189#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
190#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
191#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
192#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
193#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
194#define STM32_I2C_I2C1_IRQ_PRIORITY 5
195#define STM32_I2C_I2C2_IRQ_PRIORITY 5
196#define STM32_I2C_I2C3_IRQ_PRIORITY 5
197#define STM32_I2C_I2C1_DMA_PRIORITY 3
198#define STM32_I2C_I2C2_DMA_PRIORITY 3
199#define STM32_I2C_I2C3_DMA_PRIORITY 3
200#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
201
202/*
203 * ICU driver system settings.
204 */
205#define STM32_ICU_USE_TIM1 FALSE
206#define STM32_ICU_USE_TIM2 FALSE
207#define STM32_ICU_USE_TIM3 FALSE
208#define STM32_ICU_USE_TIM4 FALSE
209#define STM32_ICU_USE_TIM8 FALSE
210#define STM32_ICU_USE_TIM15 FALSE
211
212/*
213 * PWM driver system settings.
214 */
215#define STM32_PWM_USE_ADVANCED FALSE
216#define STM32_PWM_USE_TIM1 FALSE
217#define STM32_PWM_USE_TIM2 FALSE
218#define STM32_PWM_USE_TIM3 FALSE
219#define STM32_PWM_USE_TIM4 FALSE
220#define STM32_PWM_USE_TIM8 FALSE
221#define STM32_PWM_USE_TIM15 FALSE
222#define STM32_PWM_USE_TIM16 FALSE
223#define STM32_PWM_USE_TIM17 FALSE
224
225/*
226 * RTC driver system settings.
227 */
228
229/*
230 * SDC driver system settings.
231 */
232
233/*
234 * SERIAL driver system settings.
235 */
236#define STM32_SERIAL_USE_USART1 FALSE
237#define STM32_SERIAL_USE_USART2 FALSE
238#define STM32_SERIAL_USE_USART3 FALSE
239#define STM32_SERIAL_USE_UART4 FALSE
240#define STM32_SERIAL_USE_LPUART1 FALSE
241
242/*
243 * SPI driver system settings.
244 */
245#define STM32_SPI_USE_SPI1 FALSE
246#define STM32_SPI_USE_SPI2 FALSE
247#define STM32_SPI_USE_SPI3 FALSE
248#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
249#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
250#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
251#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
252#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
253#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
254#define STM32_SPI_SPI1_DMA_PRIORITY 1
255#define STM32_SPI_SPI2_DMA_PRIORITY 1
256#define STM32_SPI_SPI3_DMA_PRIORITY 1
257#define STM32_SPI_SPI1_IRQ_PRIORITY 10
258#define STM32_SPI_SPI2_IRQ_PRIORITY 10
259#define STM32_SPI_SPI3_IRQ_PRIORITY 10
260#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
261
262/*
263 * ST driver system settings.
264 */
265#define STM32_ST_IRQ_PRIORITY 8
266#define STM32_ST_USE_TIMER 2
267
268/*
269 * TRNG driver system settings.
270 */
271#define STM32_TRNG_USE_RNG1 FALSE
272
273/*
274 * UART driver system settings.
275 */
276#define STM32_UART_USE_USART1 FALSE
277#define STM32_UART_USE_USART2 FALSE
278#define STM32_UART_USE_USART3 FALSE
279#define STM32_UART_USE_UART4 FALSE
280#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
281#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
282#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
283#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
284#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
285#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
286#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
287#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
288#define STM32_UART_USART1_DMA_PRIORITY 0
289#define STM32_UART_USART2_DMA_PRIORITY 0
290#define STM32_UART_USART3_DMA_PRIORITY 0
291#define STM32_UART_UART4_DMA_PRIORITY 0
292#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
293
294/*
295 * USB driver system settings.
296 */
297#define STM32_USB_USE_USB1 TRUE
298#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
299#define STM32_USB_USB1_HP_IRQ_PRIORITY 5
300#define STM32_USB_USB1_LP_IRQ_PRIORITY 6
301
302/*
303 * WDG driver system settings.
304 */
305#define STM32_WDG_USE_IWDG FALSE
306
307#endif /* MCUCONF_H */
diff --git a/platforms/chibios/GENERIC_STM32_G474XE/board/board.mk b/platforms/chibios/GENERIC_STM32_G474XE/board/board.mk
new file mode 100644
index 000000000..957adf509
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G474XE/board/board.mk
@@ -0,0 +1,9 @@
1# List of all the board related files.
2BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.c
3
4# Required include directories
5BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE
6
7# Shared variables
8ALLCSRC += $(BOARDSRC)
9ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/GENERIC_STM32_G474XE/configs/config.h b/platforms/chibios/GENERIC_STM32_G474XE/configs/config.h
new file mode 100644
index 000000000..eb74d68e8
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G474XE/configs/config.h
@@ -0,0 +1,30 @@
1/* Copyright 2020 Nick Brassel (tzarc)
2 *
3 * This program is free software: you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation, either version 3 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <https://www.gnu.org/licenses/>.
15 */
16#pragma once
17
18#ifndef STM32_BOOTLOADER_DUAL_BANK
19# define STM32_BOOTLOADER_DUAL_BANK FALSE
20#endif
21
22// To Enter bootloader from `RESET` keycode, you'll need to dedicate a GPIO to
23// charge an RC network on the BOOT0 pin.
24// See the QMK Discord's #hardware channel pins for an example circuit.
25// Insert these two lines into your keyboard's `config.h` file.
26// In the case below, PB7 is selected to charge.
27#if 0
28#define STM32_BOOTLOADER_DUAL_BANK TRUE
29#define STM32_BOOTLOADER_DUAL_BANK_GPIO B7
30#endif \ No newline at end of file
diff --git a/platforms/chibios/GENERIC_STM32_G474XE/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_G474XE/configs/mcuconf.h
new file mode 100644
index 000000000..117e920e3
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_G474XE/configs/mcuconf.h
@@ -0,0 +1,372 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * STM32G4xx drivers configuration.
19 * The following settings override the default settings present in
20 * the various device driver implementation headers.
21 * Note that the settings for each driver only have effect if the whole
22 * driver is enabled in halconf.h.
23 *
24 * IRQ priorities:
25 * 15...0 Lowest...Highest.
26 *
27 * DMA priorities:
28 * 0...3 Lowest...Highest.
29 */
30
31#ifndef MCUCONF_H
32#define MCUCONF_H
33
34#define STM32G4xx_MCUCONF
35#define STM32G473_MCUCONF
36#define STM32G483_MCUCONF
37#define STM32G474_MCUCONF
38#define STM32G484_MCUCONF
39
40/*
41 * HAL driver system settings.
42 */
43#define STM32_NO_INIT FALSE
44#define STM32_VOS STM32_VOS_RANGE1
45#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
46#define STM32_PWR_CR3 (PWR_CR3_EIWF)
47#define STM32_PWR_CR4 (0U)
48#define STM32_HSI16_ENABLED TRUE
49#define STM32_HSI48_ENABLED TRUE
50#define STM32_HSE_ENABLED FALSE
51#define STM32_LSI_ENABLED FALSE
52#define STM32_LSE_ENABLED FALSE
53#define STM32_SW STM32_SW_PLLRCLK
54#define STM32_PLLSRC STM32_PLLSRC_HSI16
55#define STM32_PLLM_VALUE 2
56#define STM32_PLLN_VALUE 40
57#define STM32_PLLPDIV_VALUE 0
58#define STM32_PLLP_VALUE 7
59#define STM32_PLLQ_VALUE 2
60#define STM32_PLLR_VALUE 2
61#define STM32_HPRE STM32_HPRE_DIV1
62#define STM32_PPRE1 STM32_PPRE1_DIV1
63#define STM32_PPRE2 STM32_PPRE2_DIV1
64#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
65#define STM32_MCOPRE STM32_MCOPRE_DIV1
66#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
67
68/*
69 * Peripherals clock sources.
70 */
71#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
72#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
73#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
74#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
75#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
76#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
77#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
78#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
79#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
80#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
81#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
82#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
83#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
84#define STM32_FDCANSEL STM32_FDCANSEL_HSE
85#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
86#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
87#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
88#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
89#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
90
91/*
92 * IRQ system settings.
93 */
94#define STM32_IRQ_EXTI0_PRIORITY 6
95#define STM32_IRQ_EXTI1_PRIORITY 6
96#define STM32_IRQ_EXTI2_PRIORITY 6
97#define STM32_IRQ_EXTI3_PRIORITY 6
98#define STM32_IRQ_EXTI4_PRIORITY 6
99#define STM32_IRQ_EXTI5_9_PRIORITY 6
100#define STM32_IRQ_EXTI10_15_PRIORITY 6
101#define STM32_IRQ_EXTI164041_PRIORITY 6
102#define STM32_IRQ_EXTI17_PRIORITY 6
103#define STM32_IRQ_EXTI18_PRIORITY 6
104#define STM32_IRQ_EXTI19_PRIORITY 6
105#define STM32_IRQ_EXTI20_PRIORITY 6
106#define STM32_IRQ_EXTI212229_PRIORITY 6
107#define STM32_IRQ_EXTI30_32_PRIORITY 6
108#define STM32_IRQ_EXTI33_PRIORITY 6
109
110#define STM32_IRQ_FDCAN1_PRIORITY 10
111#define STM32_IRQ_FDCAN2_PRIORITY 10
112#define STM32_IRQ_FDCAN3_PRIORITY 10
113
114#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
115#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
116#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
117#define STM32_IRQ_TIM1_CC_PRIORITY 7
118#define STM32_IRQ_TIM2_PRIORITY 7
119#define STM32_IRQ_TIM3_PRIORITY 7
120#define STM32_IRQ_TIM4_PRIORITY 7
121#define STM32_IRQ_TIM5_PRIORITY 7
122#define STM32_IRQ_TIM6_PRIORITY 7
123#define STM32_IRQ_TIM7_PRIORITY 7
124#define STM32_IRQ_TIM8_UP_PRIORITY 7
125#define STM32_IRQ_TIM8_CC_PRIORITY 7
126#define STM32_IRQ_TIM20_UP_PRIORITY 7
127#define STM32_IRQ_TIM20_CC_PRIORITY 7
128
129#define STM32_IRQ_USART1_PRIORITY 12
130#define STM32_IRQ_USART2_PRIORITY 12
131#define STM32_IRQ_USART3_PRIORITY 12
132#define STM32_IRQ_UART4_PRIORITY 12
133#define STM32_IRQ_UART5_PRIORITY 12
134#define STM32_IRQ_LPUART1_PRIORITY 12
135
136/*
137 * ADC driver system settings.
138 */
139#define STM32_ADC_DUAL_MODE FALSE
140#define STM32_ADC_COMPACT_SAMPLES FALSE
141#define STM32_ADC_USE_ADC1 FALSE
142#define STM32_ADC_USE_ADC2 FALSE
143#define STM32_ADC_USE_ADC3 FALSE
144#define STM32_ADC_USE_ADC4 FALSE
145#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
146#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
147#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
148#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
149#define STM32_ADC_ADC1_DMA_PRIORITY 2
150#define STM32_ADC_ADC2_DMA_PRIORITY 2
151#define STM32_ADC_ADC3_DMA_PRIORITY 2
152#define STM32_ADC_ADC4_DMA_PRIORITY 2
153#define STM32_ADC_ADC12_IRQ_PRIORITY 5
154#define STM32_ADC_ADC3_IRQ_PRIORITY 5
155#define STM32_ADC_ADC4_IRQ_PRIORITY 5
156#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
157#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
158#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
159#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
160#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
161#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
162#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
163#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
164
165/*
166 * CAN driver system settings.
167 */
168#define STM32_CAN_USE_FDCAN1 FALSE
169#define STM32_CAN_USE_FDCAN2 FALSE
170#define STM32_CAN_USE_FDCAN3 FALSE
171
172/*
173 * DAC driver system settings.
174 */
175#define STM32_DAC_DUAL_MODE FALSE
176#define STM32_DAC_USE_DAC1_CH1 FALSE
177#define STM32_DAC_USE_DAC1_CH2 FALSE
178#define STM32_DAC_USE_DAC2_CH1 FALSE
179#define STM32_DAC_USE_DAC3_CH1 FALSE
180#define STM32_DAC_USE_DAC3_CH2 FALSE
181#define STM32_DAC_USE_DAC4_CH1 FALSE
182#define STM32_DAC_USE_DAC4_CH2 FALSE
183#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
184#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
185#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
186#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
187#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
188#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
189#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
190#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
191#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
192#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
193#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
194#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
195#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
196#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
197#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
198#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
199#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
200#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
201#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
202#define STM32_DAC_DAC4_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
203#define STM32_DAC_DAC4_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
204
205/*
206 * GPT driver system settings.
207 */
208#define STM32_GPT_USE_TIM1 FALSE
209#define STM32_GPT_USE_TIM2 FALSE
210#define STM32_GPT_USE_TIM3 FALSE
211#define STM32_GPT_USE_TIM4 FALSE
212#define STM32_GPT_USE_TIM5 FALSE
213#define STM32_GPT_USE_TIM6 FALSE
214#define STM32_GPT_USE_TIM7 FALSE
215#define STM32_GPT_USE_TIM8 FALSE
216#define STM32_GPT_USE_TIM15 FALSE
217#define STM32_GPT_USE_TIM16 FALSE
218#define STM32_GPT_USE_TIM17 FALSE
219
220/*
221 * I2C driver system settings.
222 */
223#define STM32_I2C_USE_I2C1 FALSE
224#define STM32_I2C_USE_I2C2 FALSE
225#define STM32_I2C_USE_I2C3 FALSE
226#define STM32_I2C_USE_I2C4 FALSE
227#define STM32_I2C_BUSY_TIMEOUT 50
228#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
229#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
230#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
231#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
232#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
233#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
234#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
235#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
236#define STM32_I2C_I2C1_IRQ_PRIORITY 5
237#define STM32_I2C_I2C2_IRQ_PRIORITY 5
238#define STM32_I2C_I2C3_IRQ_PRIORITY 5
239#define STM32_I2C_I2C4_IRQ_PRIORITY 5
240#define STM32_I2C_I2C1_DMA_PRIORITY 3
241#define STM32_I2C_I2C2_DMA_PRIORITY 3
242#define STM32_I2C_I2C3_DMA_PRIORITY 3
243#define STM32_I2C_I2C4_DMA_PRIORITY 3
244#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
245
246/*
247 * ICU driver system settings.
248 */
249#define STM32_ICU_USE_TIM1 FALSE
250#define STM32_ICU_USE_TIM2 FALSE
251#define STM32_ICU_USE_TIM3 FALSE
252#define STM32_ICU_USE_TIM4 FALSE
253#define STM32_ICU_USE_TIM5 FALSE
254#define STM32_ICU_USE_TIM8 FALSE
255#define STM32_ICU_USE_TIM15 FALSE
256#define STM32_ICU_USE_TIM16 FALSE
257#define STM32_ICU_USE_TIM17 FALSE
258
259/*
260 * PWM driver system settings.
261 */
262#define STM32_PWM_USE_ADVANCED FALSE
263#define STM32_PWM_USE_TIM1 FALSE
264#define STM32_PWM_USE_TIM2 FALSE
265#define STM32_PWM_USE_TIM3 FALSE
266#define STM32_PWM_USE_TIM4 FALSE
267#define STM32_PWM_USE_TIM5 FALSE
268#define STM32_PWM_USE_TIM8 FALSE
269#define STM32_PWM_USE_TIM15 FALSE
270#define STM32_PWM_USE_TIM16 FALSE
271#define STM32_PWM_USE_TIM17 FALSE
272#define STM32_PWM_USE_TIM20 FALSE
273
274/*
275 * RTC driver system settings.
276 */
277
278/*
279 * SDC driver system settings.
280 */
281
282/*
283 * SERIAL driver system settings.
284 */
285#define STM32_SERIAL_USE_USART1 FALSE
286#define STM32_SERIAL_USE_USART2 FALSE
287#define STM32_SERIAL_USE_USART3 FALSE
288#define STM32_SERIAL_USE_UART4 FALSE
289#define STM32_SERIAL_USE_UART5 FALSE
290#define STM32_SERIAL_USE_LPUART1 FALSE
291
292/*
293 * SPI driver system settings.
294 */
295#define STM32_SPI_USE_SPI1 FALSE
296#define STM32_SPI_USE_SPI2 FALSE
297#define STM32_SPI_USE_SPI3 FALSE
298#define STM32_SPI_USE_SPI4 FALSE
299#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
300#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
301#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
302#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
303#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
304#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
305#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
306#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
307#define STM32_SPI_SPI1_DMA_PRIORITY 1
308#define STM32_SPI_SPI2_DMA_PRIORITY 1
309#define STM32_SPI_SPI3_DMA_PRIORITY 1
310#define STM32_SPI_SPI4_DMA_PRIORITY 1
311#define STM32_SPI_SPI1_IRQ_PRIORITY 10
312#define STM32_SPI_SPI2_IRQ_PRIORITY 10
313#define STM32_SPI_SPI3_IRQ_PRIORITY 10
314#define STM32_SPI_SPI4_IRQ_PRIORITY 10
315#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
316
317/*
318 * ST driver system settings.
319 */
320#define STM32_ST_IRQ_PRIORITY 8
321#define STM32_ST_USE_TIMER 2
322
323/*
324 * TRNG driver system settings.
325 */
326#define STM32_TRNG_USE_RNG1 FALSE
327
328/*
329 * UART driver system settings.
330 */
331#define STM32_UART_USE_USART1 FALSE
332#define STM32_UART_USE_USART2 FALSE
333#define STM32_UART_USE_USART3 FALSE
334#define STM32_UART_USE_UART4 FALSE
335#define STM32_UART_USE_UART5 FALSE
336#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
337#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
338#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
339#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
340#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
341#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
342#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
343#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
344#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
345#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
346#define STM32_UART_USART1_DMA_PRIORITY 0
347#define STM32_UART_USART2_DMA_PRIORITY 0
348#define STM32_UART_USART3_DMA_PRIORITY 0
349#define STM32_UART_UART4_DMA_PRIORITY 0
350#define STM32_UART_UART5_DMA_PRIORITY 0
351#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
352
353/*
354 * USB driver system settings.
355 */
356#define STM32_USB_USE_USB1 TRUE
357#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
358#define STM32_USB_USB1_HP_IRQ_PRIORITY 5
359#define STM32_USB_USB1_LP_IRQ_PRIORITY 5
360
361/*
362 * WDG driver system settings.
363 */
364#define STM32_WDG_USE_IWDG FALSE
365
366/*
367 * WSPI driver system settings.
368 */
369#define STM32_WSPI_USE_QUADSPI1 FALSE
370#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
371
372#endif /* MCUCONF_H */
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-03 23:51:00 +0000