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-rw-r--r--tmk_core/protocol/iwrap/suart.S312
-rw-r--r--tmk_core/protocol/iwrap/suart.h16
-rw-r--r--tmk_core/protocol/iwrap/wd.h318
3 files changed, 323 insertions, 323 deletions
diff --git a/tmk_core/protocol/iwrap/suart.S b/tmk_core/protocol/iwrap/suart.S
index 1b0290963..a873515e1 100644
--- a/tmk_core/protocol/iwrap/suart.S
+++ b/tmk_core/protocol/iwrap/suart.S
@@ -1,156 +1,156 @@
1;---------------------------------------------------------------------------; 1;---------------------------------------------------------------------------;
2; Software implemented UART module ; 2; Software implemented UART module ;
3; (C)ChaN, 2005 (http://elm-chan.org/) ; 3; (C)ChaN, 2005 (http://elm-chan.org/) ;
4;---------------------------------------------------------------------------; 4;---------------------------------------------------------------------------;
5; Bit rate settings: 5; Bit rate settings:
6; 6;
7; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz 7; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
8; 2.4kbps 138 - - - - - - - - 8; 2.4kbps 138 - - - - - - - -
9; 4.8kbps 68 138 - - - - - - - 9; 4.8kbps 68 138 - - - - - - -
10; 9.6kbps 33 68 138 208 - - - - - 10; 9.6kbps 33 68 138 208 - - - - -
11; 19.2kbps - 33 68 102 138 173 208 - - 11; 19.2kbps - 33 68 102 138 173 208 - -
12; 38.4kbps - - 33 50 68 85 102 138 172 12; 38.4kbps - - 33 50 68 85 102 138 172
13; 57.6kbps - - 21 33 44 56 68 91 114 13; 57.6kbps - - 21 33 44 56 68 91 114
14; 115.2kbps - - - - 21 27 33 44 56 14; 115.2kbps - - - - 21 27 33 44 56
15 15
16.nolist 16.nolist
17#include <avr/io.h> 17#include <avr/io.h>
18.list 18.list
19 19
20#define BPS 102 /* Bit delay. (see above table) */ 20#define BPS 102 /* Bit delay. (see above table) */
21#define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */ 21#define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
22 22
23#define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */ 23#define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
24#define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */ 24#define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
25#define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */ 25#define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
26#define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */ 26#define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
27 27
28 28
29 29
30#ifdef SPM_PAGESIZE 30#ifdef SPM_PAGESIZE
31.macro _LPMI reg 31.macro _LPMI reg
32 lpm \reg, Z+ 32 lpm \reg, Z+
33.endm 33.endm
34.macro _MOVW dh,dl, sh,sl 34.macro _MOVW dh,dl, sh,sl
35 movw \dl, \sl 35 movw \dl, \sl
36.endm 36.endm
37#else 37#else
38.macro _LPMI reg 38.macro _LPMI reg
39 lpm 39 lpm
40 mov \reg, r0 40 mov \reg, r0
41 adiw ZL, 1 41 adiw ZL, 1
42.endm 42.endm
43.macro _MOVW dh,dl, sh,sl 43.macro _MOVW dh,dl, sh,sl
44 mov \dl, \sl 44 mov \dl, \sl
45 mov \dh, \sh 45 mov \dh, \sh
46.endm 46.endm
47#endif 47#endif
48 48
49 49
50 50
51;---------------------------------------------------------------------------; 51;---------------------------------------------------------------------------;
52; Transmit a byte in serial format of N81 52; Transmit a byte in serial format of N81
53; 53;
54;Prototype: void xmit (uint8_t data); 54;Prototype: void xmit (uint8_t data);
55;Size: 16 words 55;Size: 16 words
56 56
57.global xmit 57.global xmit
58.func xmit 58.func xmit
59xmit: 59xmit:
60#if BIDIR 60#if BIDIR
61 ldi r23, BPS-1 ;Pre-idle time for bidirectional data line 61 ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
625: dec r23 ; 625: dec r23 ;
63 brne 5b ;/ 63 brne 5b ;/
64#endif 64#endif
65 in r0, _SFR_IO_ADDR(SREG) ;Save flags 65 in r0, _SFR_IO_ADDR(SREG) ;Save flags
66 66
67 com r24 ;C = start bit 67 com r24 ;C = start bit
68 ldi r25, 10 ;Bit counter 68 ldi r25, 10 ;Bit counter
69 cli ;Start critical section 69 cli ;Start critical section
70 70
711: ldi r23, BPS-1 ;----- Bit transferring loop 711: ldi r23, BPS-1 ;----- Bit transferring loop
722: dec r23 ;Wait for a bit time 722: dec r23 ;Wait for a bit time
73 brne 2b ;/ 73 brne 2b ;/
74 brcs 3f ;MISO = bit to be sent 74 brcs 3f ;MISO = bit to be sent
75 OUT_1 ; 75 OUT_1 ;
763: brcc 4f ; 763: brcc 4f ;
77 OUT_0 ;/ 77 OUT_0 ;/
784: lsr r24 ;Get next bit into C 784: lsr r24 ;Get next bit into C
79 dec r25 ;All bits sent? 79 dec r25 ;All bits sent?
80 brne 1b ; no, coutinue 80 brne 1b ; no, coutinue
81 81
82 out _SFR_IO_ADDR(SREG), r0 ;End of critical section 82 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
83 ret 83 ret
84.endfunc 84.endfunc
85 85
86 86
87 87
88;---------------------------------------------------------------------------; 88;---------------------------------------------------------------------------;
89; Receive a byte 89; Receive a byte
90; 90;
91;Prototype: uint8_t rcvr (void); 91;Prototype: uint8_t rcvr (void);
92;Size: 19 words 92;Size: 19 words
93 93
94.global rcvr 94.global rcvr
95.func rcvr 95.func rcvr
96rcvr: 96rcvr:
97 in r0, _SFR_IO_ADDR(SREG) ;Save flags 97 in r0, _SFR_IO_ADDR(SREG) ;Save flags
98 98
99 ldi r24, 0x80 ;Receiving shift reg 99 ldi r24, 0x80 ;Receiving shift reg
100 cli ;Start critical section 100 cli ;Start critical section
101 101
1021: SKIP_IN_1 ;Wait for idle 1021: SKIP_IN_1 ;Wait for idle
103 rjmp 1b 103 rjmp 1b
1042: SKIP_IN_0 ;Wait for start bit 1042: SKIP_IN_0 ;Wait for start bit
105 rjmp 2b 105 rjmp 2b
106 ldi r25, BPS/2 ;Wait for half bit time 106 ldi r25, BPS/2 ;Wait for half bit time
1073: dec r25 1073: dec r25
108 brne 3b 108 brne 3b
109 109
1104: ldi r25, BPS ;----- Bit receiving loop 1104: ldi r25, BPS ;----- Bit receiving loop
1115: dec r25 ;Wait for a bit time 1115: dec r25 ;Wait for a bit time
112 brne 5b ;/ 112 brne 5b ;/
113 lsr r24 ;Next bit 113 lsr r24 ;Next bit
114 SKIP_IN_0 ;Get a data bit into r24.7 114 SKIP_IN_0 ;Get a data bit into r24.7
115 ori r24, 0x80 115 ori r24, 0x80
116 brcc 4b ;All bits received? no, continue 116 brcc 4b ;All bits received? no, continue
117 117
118 out _SFR_IO_ADDR(SREG), r0 ;End of critical section 118 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
119 ret 119 ret
120.endfunc 120.endfunc
121 121
122 122
123; Not wait for start bit. This should be called after detecting start bit. 123; Not wait for start bit. This should be called after detecting start bit.
124.global recv 124.global recv
125.func recv 125.func recv
126recv: 126recv:
127 in r0, _SFR_IO_ADDR(SREG) ;Save flags 127 in r0, _SFR_IO_ADDR(SREG) ;Save flags
128 128
129 ldi r24, 0x80 ;Receiving shift reg 129 ldi r24, 0x80 ;Receiving shift reg
130 cli ;Start critical section 130 cli ;Start critical section
131 131
132;1: SKIP_IN_1 ;Wait for idle 132;1: SKIP_IN_1 ;Wait for idle
133; rjmp 1b 133; rjmp 1b
134;2: SKIP_IN_0 ;Wait for start bit 134;2: SKIP_IN_0 ;Wait for start bit
135; rjmp 2b 135; rjmp 2b
136 ldi r25, BPS/2 ;Wait for half bit time 136 ldi r25, BPS/2 ;Wait for half bit time
1373: dec r25 1373: dec r25
138 brne 3b 138 brne 3b
139 139
1404: ldi r25, BPS ;----- Bit receiving loop 1404: ldi r25, BPS ;----- Bit receiving loop
1415: dec r25 ;Wait for a bit time 1415: dec r25 ;Wait for a bit time
142 brne 5b ;/ 142 brne 5b ;/
143 lsr r24 ;Next bit 143 lsr r24 ;Next bit
144 SKIP_IN_0 ;Get a data bit into r24.7 144 SKIP_IN_0 ;Get a data bit into r24.7
145 ori r24, 0x80 145 ori r24, 0x80
146 brcc 4b ;All bits received? no, continue 146 brcc 4b ;All bits received? no, continue
147 147
148 ldi r25, BPS/2 ;Wait for half bit time 148 ldi r25, BPS/2 ;Wait for half bit time
1496: dec r25 1496: dec r25
150 brne 6b 150 brne 6b
1517: SKIP_IN_1 ;Wait for stop bit 1517: SKIP_IN_1 ;Wait for stop bit
152 rjmp 7b 152 rjmp 7b
153 153
154 out _SFR_IO_ADDR(SREG), r0 ;End of critical section 154 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
155 ret 155 ret
156.endfunc 156.endfunc
diff --git a/tmk_core/protocol/iwrap/suart.h b/tmk_core/protocol/iwrap/suart.h
index 72725b998..7d92be069 100644
--- a/tmk_core/protocol/iwrap/suart.h
+++ b/tmk_core/protocol/iwrap/suart.h
@@ -1,8 +1,8 @@
1#ifndef SUART 1#ifndef SUART
2#define SUART 2#define SUART
3 3
4void xmit(uint8_t); 4void xmit(uint8_t);
5uint8_t rcvr(void); 5uint8_t rcvr(void);
6uint8_t recv(void); 6uint8_t recv(void);
7 7
8#endif /* SUART */ 8#endif /* SUART */
diff --git a/tmk_core/protocol/iwrap/wd.h b/tmk_core/protocol/iwrap/wd.h
index 99058f033..12395bf69 100644
--- a/tmk_core/protocol/iwrap/wd.h
+++ b/tmk_core/protocol/iwrap/wd.h
@@ -1,159 +1,159 @@
1/* This is from http://www.mtcnet.net/~henryvm/wdt/ */ 1/* This is from http://www.mtcnet.net/~henryvm/wdt/ */
2#ifndef _AVR_WD_H_ 2#ifndef _AVR_WD_H_
3#define _AVR_WD_H_ 3#define _AVR_WD_H_
4 4
5#include <avr/io.h> 5#include <avr/io.h>
6 6
7/* 7/*
8Copyright (c) 2009, Curt Van Maanen 8Copyright (c) 2009, Curt Van Maanen
9 9
10Permission to use, copy, modify, and/or distribute this software for any 10Permission to use, copy, modify, and/or distribute this software for any
11purpose with or without fee is hereby granted, provided that the above 11purpose with or without fee is hereby granted, provided that the above
12copyright notice and this permission notice appear in all copies. 12copyright notice and this permission notice appear in all copies.
13 13
14THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 21
22 22
23include usage- 23include usage-
24 #include "wd.h" //if in same directory as project 24 #include "wd.h" //if in same directory as project
25 #include <avr/wd.h> //if wd.h is in avr directory 25 #include <avr/wd.h> //if wd.h is in avr directory
26 26
27set watchdog modes and prescale 27set watchdog modes and prescale
28 28
29usage- 29usage-
30 WD_SET(mode,[timeout]); //prescale always set 30 WD_SET(mode,[timeout]); //prescale always set
31 31
32modes- 32modes-
33 WD_OFF disabled 33 WD_OFF disabled
34 WD_RST normal reset mode 34 WD_RST normal reset mode
35 WD_IRQ interrupt only mode (if supported) 35 WD_IRQ interrupt only mode (if supported)
36 WD_RST_IRQ interrupt+reset mode (if supported) 36 WD_RST_IRQ interrupt+reset mode (if supported)
37 37
38timeout- 38timeout-
39 WDTO_15MS default if no timeout provided 39 WDTO_15MS default if no timeout provided
40 WDTO_30MS 40 WDTO_30MS
41 WDTO_60MS 41 WDTO_60MS
42 WDTO_120MS 42 WDTO_120MS
43 WDTO_250MS 43 WDTO_250MS
44 WDTO_500MS 44 WDTO_500MS
45 WDTO_1S 45 WDTO_1S
46 WDTO_2S 46 WDTO_2S
47 WDTO_4S (if supported) 47 WDTO_4S (if supported)
48 WDTO_8S (if supported) 48 WDTO_8S (if supported)
49 49
50examples- 50examples-
51 WD_SET(WD_RST,WDTO_1S); //reset mode, 1s timeout 51 WD_SET(WD_RST,WDTO_1S); //reset mode, 1s timeout
52 WD_SET(WD_OFF); //watchdog disabled (if not fused on) 52 WD_SET(WD_OFF); //watchdog disabled (if not fused on)
53 WD_SET(WD_RST); //reset mode, 15ms (default timeout) 53 WD_SET(WD_RST); //reset mode, 15ms (default timeout)
54 WD_SET(WD_IRQ,WDTO_120MS); //interrupt only mode, 120ms timeout 54 WD_SET(WD_IRQ,WDTO_120MS); //interrupt only mode, 120ms timeout
55 WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout 55 WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout
56 56
57 57
58for enhanced watchdogs, if the watchdog is not being used WDRF should be 58for enhanced watchdogs, if the watchdog is not being used WDRF should be
59cleared on every power up or reset, along with disabling the watchdog- 59cleared on every power up or reset, along with disabling the watchdog-
60 WD_DISABLE(); //clear WDRF, then turn off watchdog 60 WD_DISABLE(); //clear WDRF, then turn off watchdog
61 61
62*/ 62*/
63 63
64//reset registers to the same name (MCUCSR) 64//reset registers to the same name (MCUCSR)
65#if !defined(MCUCSR) 65#if !defined(MCUCSR)
66#define MCUCSR MCUSR 66#define MCUCSR MCUSR
67#endif 67#endif
68 68
69//watchdog registers to the same name (WDTCSR) 69//watchdog registers to the same name (WDTCSR)
70#if !defined(WDTCSR) 70#if !defined(WDTCSR)
71#define WDTCSR WDTCR 71#define WDTCSR WDTCR
72#endif 72#endif
73 73
74//if enhanced watchdog, define irq values, create disable macro 74//if enhanced watchdog, define irq values, create disable macro
75#if defined(WDIF) 75#if defined(WDIF)
76#define WD_IRQ 0xC0 76#define WD_IRQ 0xC0
77#define WD_RST_IRQ 0xC8 77#define WD_RST_IRQ 0xC8
78#define WD_DISABLE() do{ \ 78#define WD_DISABLE() do{ \
79 MCUCSR &= ~(1<<WDRF); \ 79 MCUCSR &= ~(1<<WDRF); \
80 WD_SET(WD_OFF); \ 80 WD_SET(WD_OFF); \
81 }while(0) 81 }while(0)
82#endif 82#endif
83 83
84//all watchdogs 84//all watchdogs
85#define WD_RST 8 85#define WD_RST 8
86#define WD_OFF 0 86#define WD_OFF 0
87 87
88//prescale values 88//prescale values
89#define WDTO_15MS 0 89#define WDTO_15MS 0
90#define WDTO_30MS 1 90#define WDTO_30MS 1
91#define WDTO_60MS 2 91#define WDTO_60MS 2
92#define WDTO_120MS 3 92#define WDTO_120MS 3
93#define WDTO_250MS 4 93#define WDTO_250MS 4
94#define WDTO_500MS 5 94#define WDTO_500MS 5
95#define WDTO_1S 6 95#define WDTO_1S 6
96#define WDTO_2S 7 96#define WDTO_2S 7
97 97
98//prescale values for avrs with WDP3 98//prescale values for avrs with WDP3
99#if defined(WDP3) 99#if defined(WDP3)
100#define WDTO_4S 0x20 100#define WDTO_4S 0x20
101#define WDTO_8S 0x21 101#define WDTO_8S 0x21
102#endif 102#endif
103 103
104//watchdog reset 104//watchdog reset
105#define WDR() __asm__ __volatile__("wdr") 105#define WDR() __asm__ __volatile__("wdr")
106 106
107//avr reset using watchdog 107//avr reset using watchdog
108#define WD_AVR_RESET() do{ \ 108#define WD_AVR_RESET() do{ \
109 __asm__ __volatile__("cli"); \ 109 __asm__ __volatile__("cli"); \
110 WD_SET_UNSAFE(WD_RST); \ 110 WD_SET_UNSAFE(WD_RST); \
111 while(1); \ 111 while(1); \
112 }while(0) 112 }while(0)
113 113
114/*set the watchdog- 114/*set the watchdog-
1151. save SREG 1151. save SREG
1162. turn off irq's 1162. turn off irq's
1173. reset watchdog timer 1173. reset watchdog timer
1184. enable watchdog change 1184. enable watchdog change
1195. write watchdog value 1195. write watchdog value
1206. restore SREG (restoring irq status) 1206. restore SREG (restoring irq status)
121*/ 121*/
122#define WD_SET(val,...) \ 122#define WD_SET(val,...) \
123 __asm__ __volatile__( \ 123 __asm__ __volatile__( \
124 "in __tmp_reg__,__SREG__" "\n\t" \ 124 "in __tmp_reg__,__SREG__" "\n\t" \
125 "cli" "\n\t" \ 125 "cli" "\n\t" \
126 "wdr" "\n\t" \ 126 "wdr" "\n\t" \
127 "sts %[wdreg],%[wden]" "\n\t" \ 127 "sts %[wdreg],%[wden]" "\n\t" \
128 "sts %[wdreg],%[wdval]" "\n\t" \ 128 "sts %[wdreg],%[wdval]" "\n\t" \
129 "out __SREG__,__tmp_reg__" "\n\t" \ 129 "out __SREG__,__tmp_reg__" "\n\t" \
130 : \ 130 : \
131 : [wdreg] "M" (&WDTCSR), \ 131 : [wdreg] "M" (&WDTCSR), \
132 [wden] "r" ((uint8_t)(0x18)), \ 132 [wden] "r" ((uint8_t)(0x18)), \
133 [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \ 133 [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
134 : "r0" \ 134 : "r0" \
135) 135)
136 136
137/*set the watchdog when I bit in SREG known to be clear- 137/*set the watchdog when I bit in SREG known to be clear-
1381. reset watchdog timer 1381. reset watchdog timer
1392. enable watchdog change 1392. enable watchdog change
1405. write watchdog value 1405. write watchdog value
141*/ 141*/
142#define WD_SET_UNSAFE(val,...) \ 142#define WD_SET_UNSAFE(val,...) \
143 __asm__ __volatile__( \ 143 __asm__ __volatile__( \
144 "wdr" "\n\t" \ 144 "wdr" "\n\t" \
145 "sts %[wdreg],%[wden]" "\n\t" \ 145 "sts %[wdreg],%[wden]" "\n\t" \
146 "sts %[wdreg],%[wdval]" "\n\t" \ 146 "sts %[wdreg],%[wdval]" "\n\t" \
147 : \ 147 : \
148 : [wdreg] "M" (&WDTCSR), \ 148 : [wdreg] "M" (&WDTCSR), \
149 [wden] "r" ((uint8_t)(0x18)), \ 149 [wden] "r" ((uint8_t)(0x18)), \
150 [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \ 150 [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
151) 151)
152 152
153 153
154//for compatibility with avr/wdt.h 154//for compatibility with avr/wdt.h
155#define wdt_enable(val) WD_SET(WD_RST,val) 155#define wdt_enable(val) WD_SET(WD_RST,val)
156#define wdt_disable() WD_SET(WD_OFF) 156#define wdt_disable() WD_SET(WD_OFF)
157 157
158 158
159#endif /* _AVR_WD_H_ */ 159#endif /* _AVR_WD_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-22 02:29:19 +0000