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-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/board/board.c242
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/board/board.h475
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/board/board.mk9
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h7
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h714
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h525
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h273
-rw-r--r--platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk9
8 files changed, 2254 insertions, 0 deletions
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.c b/platforms/chibios/GENERIC_STM32_F303XC/board/board.c
new file mode 100644
index 000000000..4722acd64
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.c
@@ -0,0 +1,242 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#include "hal.h"
23#include "stm32_gpio.h"
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Driver exported variables. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver local variables and types. */
35/*===========================================================================*/
36
37/**
38 * @brief Type of STM32 GPIO port setup.
39 */
40typedef struct {
41 uint32_t moder;
42 uint32_t otyper;
43 uint32_t ospeedr;
44 uint32_t pupdr;
45 uint32_t odr;
46 uint32_t afrl;
47 uint32_t afrh;
48} gpio_setup_t;
49
50/**
51 * @brief Type of STM32 GPIO initialization data.
52 */
53typedef struct {
54#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
55 gpio_setup_t PAData;
56#endif
57#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
58 gpio_setup_t PBData;
59#endif
60#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
61 gpio_setup_t PCData;
62#endif
63#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
64 gpio_setup_t PDData;
65#endif
66#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
67 gpio_setup_t PEData;
68#endif
69#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
70 gpio_setup_t PFData;
71#endif
72#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
73 gpio_setup_t PGData;
74#endif
75#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
76 gpio_setup_t PHData;
77#endif
78#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
79 gpio_setup_t PIData;
80#endif
81#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
82 gpio_setup_t PJData;
83#endif
84#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
85 gpio_setup_t PKData;
86#endif
87} gpio_config_t;
88
89/**
90 * @brief STM32 GPIO static initialization data.
91 */
92static const gpio_config_t gpio_default_config = {
93#if STM32_HAS_GPIOA
94 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
95#endif
96#if STM32_HAS_GPIOB
97 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
98#endif
99#if STM32_HAS_GPIOC
100 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
101#endif
102#if STM32_HAS_GPIOD
103 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
104#endif
105#if STM32_HAS_GPIOE
106 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
107#endif
108#if STM32_HAS_GPIOF
109 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
110#endif
111#if STM32_HAS_GPIOG
112 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
113#endif
114#if STM32_HAS_GPIOH
115 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
116#endif
117#if STM32_HAS_GPIOI
118 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
119#endif
120#if STM32_HAS_GPIOJ
121 {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
122#endif
123#if STM32_HAS_GPIOK
124 {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
125#endif
126};
127
128/*===========================================================================*/
129/* Driver local functions. */
130/*===========================================================================*/
131
132static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
133 gpiop->OTYPER = config->otyper;
134 gpiop->OSPEEDR = config->ospeedr;
135 gpiop->PUPDR = config->pupdr;
136 gpiop->ODR = config->odr;
137 gpiop->AFRL = config->afrl;
138 gpiop->AFRH = config->afrh;
139 gpiop->MODER = config->moder;
140}
141
142static void stm32_gpio_init(void) {
143 /* Enabling GPIO-related clocks, the mask comes from the
144 registry header file.*/
145 rccResetAHB(STM32_GPIO_EN_MASK);
146 rccEnableAHB(STM32_GPIO_EN_MASK, true);
147
148 /* Initializing all the defined GPIO ports.*/
149#if STM32_HAS_GPIOA
150 gpio_init(GPIOA, &gpio_default_config.PAData);
151#endif
152#if STM32_HAS_GPIOB
153 gpio_init(GPIOB, &gpio_default_config.PBData);
154#endif
155#if STM32_HAS_GPIOC
156 gpio_init(GPIOC, &gpio_default_config.PCData);
157#endif
158#if STM32_HAS_GPIOD
159 gpio_init(GPIOD, &gpio_default_config.PDData);
160#endif
161#if STM32_HAS_GPIOE
162 gpio_init(GPIOE, &gpio_default_config.PEData);
163#endif
164#if STM32_HAS_GPIOF
165 gpio_init(GPIOF, &gpio_default_config.PFData);
166#endif
167#if STM32_HAS_GPIOG
168 gpio_init(GPIOG, &gpio_default_config.PGData);
169#endif
170#if STM32_HAS_GPIOH
171 gpio_init(GPIOH, &gpio_default_config.PHData);
172#endif
173#if STM32_HAS_GPIOI
174 gpio_init(GPIOI, &gpio_default_config.PIData);
175#endif
176#if STM32_HAS_GPIOJ
177 gpio_init(GPIOJ, &gpio_default_config.PJData);
178#endif
179#if STM32_HAS_GPIOK
180 gpio_init(GPIOK, &gpio_default_config.PKData);
181#endif
182}
183
184__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
185
186/**
187 * @brief Early initialization code.
188 * @details This initialization must be performed just after stack setup
189 * and before any other initialization.
190 */
191void __early_init(void) {
192 enter_bootloader_mode_if_requested();
193
194 stm32_gpio_init();
195 stm32_clock_init();
196}
197
198#if HAL_USE_SDC || defined(__DOXYGEN__)
199/**
200 * @brief SDC card detection.
201 */
202bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
203 (void)sdcp;
204 /* TODO: Fill the implementation.*/
205 return true;
206}
207
208/**
209 * @brief SDC card write protection detection.
210 */
211bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
212 (void)sdcp;
213 /* TODO: Fill the implementation.*/
214 return false;
215}
216#endif /* HAL_USE_SDC */
217
218#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
219/**
220 * @brief MMC_SPI card detection.
221 */
222bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
223 (void)mmcp;
224 /* TODO: Fill the implementation.*/
225 return true;
226}
227
228/**
229 * @brief MMC_SPI card write protection detection.
230 */
231bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
232 (void)mmcp;
233 /* TODO: Fill the implementation.*/
234 return false;
235}
236#endif
237
238/**
239 * @brief Board-specific initialization code.
240 * @todo Add your board-specific code, if any.
241 */
242void boardInit(void) {}
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.h b/platforms/chibios/GENERIC_STM32_F303XC/board/board.h
new file mode 100644
index 000000000..3579c8277
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.h
@@ -0,0 +1,475 @@
1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#ifndef _BOARD_H_
18#define _BOARD_H_
19
20/*
21 * Setup for Generic STM32_F303 Board
22 */
23
24/*
25 * Board identifier.
26 */
27#define BOARD_GENERIC_STM32_F303XC
28#define BOARD_NAME "STM32_F303"
29
30/*
31 * Board oscillators-related settings.
32 * NOTE: LSE not fitted.
33 */
34#if !defined(STM32_LSECLK)
35# define STM32_LSECLK 0U
36#endif
37
38#define STM32_LSEDRV (3U << 3U)
39
40#if !defined(STM32_HSECLK)
41# define STM32_HSECLK 8000000U
42#endif
43
44// #define STM32_HSE_BYPASS
45
46/*
47 * MCU type as defined in the ST header.
48 */
49#define STM32F303xC
50
51/*
52 * IO pins assignments.
53 */
54#define GPIOA_PIN0 0U
55#define GPIOA_PIN1 1U
56#define GPIOA_PIN2 2U
57#define GPIOA_PIN3 3U
58#define GPIOA_PIN4 4U
59#define GPIOA_PIN5 5U
60#define GPIOA_PIN6 6U
61#define GPIOA_PIN7 7U
62#define GPIOA_PIN8 8U
63#define GPIOA_PIN9 9U
64#define GPIOA_PIN10 10U
65#define GPIOA_USB_DM 11U
66#define GPIOA_USB_DP 12U
67#define GPIOA_SWDIO 13U
68#define GPIOA_SWCLK 14U
69#define GPIOA_PIN15 15U
70
71#define GPIOB_PIN0 0U
72#define GPIOB_PIN1 1U
73#define GPIOB_PIN2 2U
74#define GPIOB_PIN3 3U
75#define GPIOB_PIN4 4U
76#define GPIOB_PIN5 5U
77#define GPIOB_PIN6 6U
78#define GPIOB_PIN7 7U
79#define GPIOB_PIN8 8U
80#define GPIOB_PIN9 9U
81#define GPIOB_PIN10 10U
82#define GPIOB_PIN11 11U
83#define GPIOB_PIN12 12U
84#define GPIOB_PIN13 13U
85#define GPIOB_PIN14 14U
86#define GPIOB_PIN15 15U
87
88#define GPIOC_PIN0 0U
89#define GPIOC_PIN1 1U
90#define GPIOC_PIN2 2U
91#define GPIOC_PIN3 3U
92#define GPIOC_PIN4 4U
93#define GPIOC_PIN5 5U
94#define GPIOC_PIN6 6U
95#define GPIOC_PIN7 7U
96#define GPIOC_PIN8 8U
97#define GPIOC_PIN9 9U
98#define GPIOC_PIN10 10U
99#define GPIOC_PIN11 11U
100#define GPIOC_PIN12 12U
101#define GPIOC_PIN13 13U
102#define GPIOC_PIN14 14U
103#define GPIOC_PIN15 15U
104
105#define GPIOD_PIN0 0U
106#define GPIOD_PIN1 1U
107#define GPIOD_PIN2 2U
108#define GPIOD_PIN3 3U
109#define GPIOD_PIN4 4U
110#define GPIOD_PIN5 5U
111#define GPIOD_PIN6 6U
112#define GPIOD_PIN7 7U
113#define GPIOD_PIN8 8U
114#define GPIOD_PIN9 9U
115#define GPIOD_PIN10 10U
116#define GPIOD_PIN11 11U
117#define GPIOD_PIN12 12U
118#define GPIOD_PIN13 13U
119#define GPIOD_PIN14 14U
120#define GPIOD_PIN15 15U
121
122#define GPIOE_PIN0 0U
123#define GPIOE_PIN1 1U
124#define GPIOE_PIN2 2U
125#define GPIOE_PIN3 3U
126#define GPIOE_PIN4 4U
127#define GPIOE_PIN5 5U
128#define GPIOE_PIN6 6U
129#define GPIOE_PIN7 7U
130#define GPIOE_PIN8 8U
131#define GPIOE_PIN9 9U
132#define GPIOE_PIN10 10U
133#define GPIOE_PIN11 11U
134#define GPIOE_PIN12 12U
135#define GPIOE_PIN13 13U
136#define GPIOE_PIN14 14U
137#define GPIOE_PIN15 15U
138
139#define GPIOF_I2C2_SDA 0U
140#define GPIOF_I2C2_SCL 1U
141#define GPIOF_PIN2 2U
142#define GPIOF_PIN3 3U
143#define GPIOF_PIN4 4U
144#define GPIOF_PIN5 5U
145#define GPIOF_PIN6 6U
146#define GPIOF_PIN7 7U
147#define GPIOF_PIN8 8U
148#define GPIOF_PIN9 9U
149#define GPIOF_PIN10 10U
150#define GPIOF_PIN11 11U
151#define GPIOF_PIN12 12U
152#define GPIOF_PIN13 13U
153#define GPIOF_PIN14 14U
154#define GPIOF_PIN15 15U
155
156#define GPIOG_PIN0 0U
157#define GPIOG_PIN1 1U
158#define GPIOG_PIN2 2U
159#define GPIOG_PIN3 3U
160#define GPIOG_PIN4 4U
161#define GPIOG_PIN5 5U
162#define GPIOG_PIN6 6U
163#define GPIOG_PIN7 7U
164#define GPIOG_PIN8 8U
165#define GPIOG_PIN9 9U
166#define GPIOG_PIN10 10U
167#define GPIOG_PIN11 11U
168#define GPIOG_PIN12 12U
169#define GPIOG_PIN13 13U
170#define GPIOG_PIN14 14U
171#define GPIOG_PIN15 15U
172
173#define GPIOH_PIN0 0U
174#define GPIOH_PIN1 1U
175#define GPIOH_PIN2 2U
176#define GPIOH_PIN3 3U
177#define GPIOH_PIN4 4U
178#define GPIOH_PIN5 5U
179#define GPIOH_PIN6 6U
180#define GPIOH_PIN7 7U
181#define GPIOH_PIN8 8U
182#define GPIOH_PIN9 9U
183#define GPIOH_PIN10 10U
184#define GPIOH_PIN11 11U
185#define GPIOH_PIN12 12U
186#define GPIOH_PIN13 13U
187#define GPIOH_PIN14 14U
188#define GPIOH_PIN15 15U
189
190/*
191 * IO lines assignments.
192 */
193#define LINE_L3GD20_SDI PAL_LINE(GPIOA, 7U)
194#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
195#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
196#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
197#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
198
199#define LINE_PIN6 PAL_LINE(GPIOF, 0U)
200#define LINE_PIN7 PAL_LINE(GPIOF, 1U)
201
202#define LINE_CAPS_LOCK PAL_LINE(GPIOB, 7U)
203
204/*
205 * I/O ports initial setup, this configuration is established soon after reset
206 * in the initialization code.
207 * Please refer to the STM32 Reference Manual for details.
208 */
209#define PIN_MODE_INPUT(n) (0U << ((n)*2U))
210#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U))
211#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U))
212#define PIN_MODE_ANALOG(n) (3U << ((n)*2U))
213#define PIN_ODR_LOW(n) (0U << (n))
214#define PIN_ODR_HIGH(n) (1U << (n))
215#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
216#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
217#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U))
218#define PIN_OSPEED_LOW(n) (1U << ((n)*2U))
219#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U))
220#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U))
221#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U))
222#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U))
223#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U))
224#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
225
226/*
227 * GPIOA setup:
228 *
229 * PA0 - NC
230 * PA1 - NC
231 * PA2 - COL1
232 * PA3 - COL2
233 * PA4 - SPEAKER1
234 * PA5 - SPEAKER2
235 * PA6 - COL3
236 * PA7 - COL8
237 * PA8 - COL6
238 * PA9 - COL7
239 * PA10 - ROW5
240 * PA11 - USB_DM (alternate 14).
241 * PA12 - USB_DP (alternate 14).
242 * PA13 - SWDIO (alternate 0).
243 * PA14 - SWCLK (alternate 0).
244 * PA15 - ROW4
245 */
246#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | PIN_MODE_ALTERNATE(GPIOA_PIN1) | PIN_MODE_INPUT(GPIOA_PIN2) | PIN_MODE_INPUT(GPIOA_PIN3) | PIN_MODE_INPUT(GPIOA_PIN4) | PIN_MODE_INPUT(GPIOA_PIN5) | PIN_MODE_INPUT(GPIOA_PIN6) | PIN_MODE_INPUT(GPIOA_PIN7) | PIN_MODE_INPUT(GPIOA_PIN8) | PIN_MODE_INPUT(GPIOA_PIN9) | PIN_MODE_INPUT(GPIOA_PIN10) | PIN_MODE_ALTERNATE(GPIOA_USB_DM) | PIN_MODE_ALTERNATE(GPIOA_USB_DP) | PIN_MODE_ALTERNATE(GPIOA_SWDIO) | PIN_MODE_ALTERNATE(GPIOA_SWCLK) | PIN_MODE_INPUT(GPIOA_PIN15))
247#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
248#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | PIN_OSPEED_HIGH(GPIOA_PIN1) | PIN_OSPEED_VERYLOW(GPIOA_PIN2) | PIN_OSPEED_VERYLOW(GPIOA_PIN3) | PIN_OSPEED_VERYLOW(GPIOA_PIN4) | PIN_OSPEED_VERYLOW(GPIOA_PIN5) | PIN_OSPEED_VERYLOW(GPIOA_PIN6) | PIN_OSPEED_VERYLOW(GPIOA_PIN7) | PIN_OSPEED_VERYLOW(GPIOA_PIN8) | PIN_OSPEED_VERYLOW(GPIOA_PIN9) | PIN_OSPEED_VERYLOW(GPIOA_PIN10) | PIN_OSPEED_HIGH(GPIOA_USB_DM) | PIN_OSPEED_VERYLOW(GPIOA_USB_DP) | PIN_OSPEED_HIGH(GPIOA_SWDIO) | PIN_OSPEED_HIGH(GPIOA_SWCLK) | PIN_OSPEED_VERYLOW(GPIOA_PIN15))
249#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | PIN_PUPDR_FLOATING(GPIOA_PIN1) | PIN_PUPDR_PULLUP(GPIOA_PIN2) | PIN_PUPDR_PULLUP(GPIOA_PIN3) | PIN_PUPDR_PULLUP(GPIOA_PIN4) | PIN_PUPDR_PULLUP(GPIOA_PIN5) | PIN_PUPDR_PULLUP(GPIOA_PIN6) | PIN_PUPDR_FLOATING(GPIOA_PIN7) | PIN_PUPDR_PULLUP(GPIOA_PIN8) | PIN_PUPDR_PULLUP(GPIOA_PIN9) | PIN_PUPDR_PULLUP(GPIOA_PIN10) | PIN_PUPDR_FLOATING(GPIOA_USB_DM) | PIN_PUPDR_FLOATING(GPIOA_USB_DP) | PIN_PUPDR_PULLUP(GPIOA_SWDIO) | PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | PIN_PUPDR_PULLUP(GPIOA_PIN15))
250#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | PIN_ODR_HIGH(GPIOA_PIN1) | PIN_ODR_HIGH(GPIOA_PIN2) | PIN_ODR_HIGH(GPIOA_PIN3) | PIN_ODR_HIGH(GPIOA_PIN4) | PIN_ODR_HIGH(GPIOA_PIN5) | PIN_ODR_HIGH(GPIOA_PIN6) | PIN_ODR_HIGH(GPIOA_PIN7) | PIN_ODR_HIGH(GPIOA_PIN8) | PIN_ODR_HIGH(GPIOA_PIN9) | PIN_ODR_HIGH(GPIOA_PIN10) | PIN_ODR_HIGH(GPIOA_USB_DM) | PIN_ODR_HIGH(GPIOA_USB_DP) | PIN_ODR_HIGH(GPIOA_SWDIO) | PIN_ODR_HIGH(GPIOA_SWCLK) | PIN_ODR_HIGH(GPIOA_PIN15))
251#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | PIN_AFIO_AF(GPIOA_PIN1, 1) | PIN_AFIO_AF(GPIOA_PIN2, 0) | PIN_AFIO_AF(GPIOA_PIN3, 0) | PIN_AFIO_AF(GPIOA_PIN4, 0) | PIN_AFIO_AF(GPIOA_PIN5, 5) | PIN_AFIO_AF(GPIOA_PIN6, 5) | PIN_AFIO_AF(GPIOA_PIN7, 5))
252#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | PIN_AFIO_AF(GPIOA_PIN9, 0) | PIN_AFIO_AF(GPIOA_PIN10, 0) | PIN_AFIO_AF(GPIOA_USB_DM, 14) | PIN_AFIO_AF(GPIOA_USB_DP, 14) | PIN_AFIO_AF(GPIOA_SWDIO, 0) | PIN_AFIO_AF(GPIOA_SWCLK, 0) | PIN_AFIO_AF(GPIOA_PIN15, 0))
253
254/*
255 * GPIOB setup:
256 *
257 * PB0 - PIN0 (input pullup).
258 * PB1 - PIN1 (input pullup).
259 * PB2 - PIN2 (input pullup).
260 * PB3 - PIN3 (alternate 0).
261 * PB4 - PIN4 (input pullup).
262 * PB5 - PIN5 (input pullup).
263 * PB6 - PIN6 LSM303DLHC_SCL (alternate 4).
264 * PB7 - PIN7 LSM303DLHC_SDA (alternate 4).
265 * PB8 - PIN8 (input pullup).
266 * PB9 - PIN9 (input pullup).
267 * PB10 - PIN10 (input pullup).
268 * PB11 - PIN11 (input pullup).
269 * PB12 - PIN12 (input pullup).
270 * PB13 - PIN13 (input pullup).
271 * PB14 - PIN14 (input pullup).
272 * PB15 - PIN15 (input pullup).
273 */
274#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | PIN_MODE_INPUT(GPIOB_PIN1) | PIN_MODE_INPUT(GPIOB_PIN2) | PIN_MODE_ALTERNATE(GPIOB_PIN3) | PIN_MODE_INPUT(GPIOB_PIN4) | PIN_MODE_INPUT(GPIOB_PIN5) | PIN_MODE_ALTERNATE(GPIOB_PIN6) | PIN_MODE_OUTPUT(GPIOB_PIN7) | PIN_MODE_INPUT(GPIOB_PIN8) | PIN_MODE_INPUT(GPIOB_PIN9) | PIN_MODE_INPUT(GPIOB_PIN10) | PIN_MODE_INPUT(GPIOB_PIN11) | PIN_MODE_INPUT(GPIOB_PIN12) | PIN_MODE_INPUT(GPIOB_PIN13) | PIN_MODE_INPUT(GPIOB_PIN14) | PIN_MODE_INPUT(GPIOB_PIN15))
275#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | PIN_OTYPE_OPENDRAIN(GPIOB_PIN6) | PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
276#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | PIN_OSPEED_VERYLOW(GPIOB_PIN1) | PIN_OSPEED_VERYLOW(GPIOB_PIN2) | PIN_OSPEED_HIGH(GPIOB_PIN3) | PIN_OSPEED_VERYLOW(GPIOB_PIN4) | PIN_OSPEED_VERYLOW(GPIOB_PIN5) | PIN_OSPEED_HIGH(GPIOB_PIN6) | PIN_OSPEED_VERYLOW(GPIOB_PIN7) | PIN_OSPEED_VERYLOW(GPIOB_PIN8) | PIN_OSPEED_VERYLOW(GPIOB_PIN9) | PIN_OSPEED_VERYLOW(GPIOB_PIN10) | PIN_OSPEED_VERYLOW(GPIOB_PIN11) | PIN_OSPEED_VERYLOW(GPIOB_PIN12) | PIN_OSPEED_VERYLOW(GPIOB_PIN13) | PIN_OSPEED_VERYLOW(GPIOB_PIN14) | PIN_OSPEED_VERYLOW(GPIOB_PIN15))
277#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | PIN_PUPDR_PULLUP(GPIOB_PIN1) | PIN_PUPDR_PULLUP(GPIOB_PIN2) | PIN_PUPDR_FLOATING(GPIOB_PIN3) | PIN_PUPDR_PULLUP(GPIOB_PIN4) | PIN_PUPDR_PULLUP(GPIOB_PIN5) | PIN_PUPDR_FLOATING(GPIOB_PIN6) | PIN_PUPDR_PULLDOWN(GPIOB_PIN7) | PIN_PUPDR_PULLUP(GPIOB_PIN8) | PIN_PUPDR_PULLUP(GPIOB_PIN9) | PIN_PUPDR_PULLUP(GPIOB_PIN10) | PIN_PUPDR_PULLUP(GPIOB_PIN11) | PIN_PUPDR_PULLUP(GPIOB_PIN12) | PIN_PUPDR_PULLUP(GPIOB_PIN13) | PIN_PUPDR_PULLUP(GPIOB_PIN14) | PIN_PUPDR_PULLUP(GPIOB_PIN15))
278#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | PIN_ODR_HIGH(GPIOB_PIN1) | PIN_ODR_HIGH(GPIOB_PIN2) | PIN_ODR_HIGH(GPIOB_PIN3) | PIN_ODR_HIGH(GPIOB_PIN4) | PIN_ODR_HIGH(GPIOB_PIN5) | PIN_ODR_HIGH(GPIOB_PIN6) | PIN_ODR_LOW(GPIOB_PIN7) | PIN_ODR_HIGH(GPIOB_PIN8) | PIN_ODR_HIGH(GPIOB_PIN9) | PIN_ODR_HIGH(GPIOB_PIN10) | PIN_ODR_HIGH(GPIOB_PIN11) | PIN_ODR_HIGH(GPIOB_PIN12) | PIN_ODR_HIGH(GPIOB_PIN13) | PIN_ODR_HIGH(GPIOB_PIN14) | PIN_ODR_HIGH(GPIOB_PIN15))
279#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | PIN_AFIO_AF(GPIOB_PIN1, 0) | PIN_AFIO_AF(GPIOB_PIN2, 0) | PIN_AFIO_AF(GPIOB_PIN3, 0) | PIN_AFIO_AF(GPIOB_PIN4, 0) | PIN_AFIO_AF(GPIOB_PIN5, 0) | PIN_AFIO_AF(GPIOB_PIN6, 4) | PIN_AFIO_AF(GPIOB_PIN7, 0))
280#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | PIN_AFIO_AF(GPIOB_PIN9, 0) | PIN_AFIO_AF(GPIOB_PIN10, 0) | PIN_AFIO_AF(GPIOB_PIN11, 0) | PIN_AFIO_AF(GPIOB_PIN12, 0) | PIN_AFIO_AF(GPIOB_PIN13, 0) | PIN_AFIO_AF(GPIOB_PIN14, 0) | PIN_AFIO_AF(GPIOB_PIN15, 0))
281
282/*
283 * GPIOC setup:
284 *
285 * PC0 - PIN0 (input pullup).
286 * PC1 - PIN1 (input pullup).
287 * PC2 - PIN2 (input pullup).
288 * PC3 - PIN3 (input pullup).
289 * PC4 - PIN4 (input pullup).
290 * PC5 - PIN5 (input pullup).
291 * PC6 - PIN6 (input pullup).
292 * PC7 - PIN7 (input pullup).
293 * PC8 - PIN8 (input pullup).
294 * PC9 - PIN9 (input pullup).
295 * PC10 - PIN10 (input pullup).
296 * PC11 - PIN11 (input pullup).
297 * PC12 - PIN12 (input pullup).
298 * PC13 - PIN13 (input pullup).
299 * PC14 - PIN14 (input floating).
300 * PC15 - PIN15 (input floating).
301 */
302#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | PIN_MODE_INPUT(GPIOC_PIN1) | PIN_MODE_INPUT(GPIOC_PIN2) | PIN_MODE_INPUT(GPIOC_PIN3) | PIN_MODE_INPUT(GPIOC_PIN4) | PIN_MODE_INPUT(GPIOC_PIN5) | PIN_MODE_INPUT(GPIOC_PIN6) | PIN_MODE_INPUT(GPIOC_PIN7) | PIN_MODE_INPUT(GPIOC_PIN8) | PIN_MODE_INPUT(GPIOC_PIN9) | PIN_MODE_INPUT(GPIOC_PIN10) | PIN_MODE_INPUT(GPIOC_PIN11) | PIN_MODE_INPUT(GPIOC_PIN12) | PIN_MODE_INPUT(GPIOC_PIN13) | PIN_MODE_INPUT(GPIOC_PIN14) | PIN_MODE_INPUT(GPIOC_PIN15))
303#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
304#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | PIN_OSPEED_VERYLOW(GPIOC_PIN1) | PIN_OSPEED_VERYLOW(GPIOC_PIN2) | PIN_OSPEED_VERYLOW(GPIOC_PIN3) | PIN_OSPEED_VERYLOW(GPIOC_PIN4) | PIN_OSPEED_VERYLOW(GPIOC_PIN5) | PIN_OSPEED_VERYLOW(GPIOC_PIN6) | PIN_OSPEED_VERYLOW(GPIOC_PIN7) | PIN_OSPEED_VERYLOW(GPIOC_PIN8) | PIN_OSPEED_VERYLOW(GPIOC_PIN9) | PIN_OSPEED_VERYLOW(GPIOC_PIN10) | PIN_OSPEED_VERYLOW(GPIOC_PIN11) | PIN_OSPEED_VERYLOW(GPIOC_PIN12) | PIN_OSPEED_VERYLOW(GPIOC_PIN13) | PIN_OSPEED_HIGH(GPIOC_PIN14) | PIN_OSPEED_HIGH(GPIOC_PIN15))
305#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | PIN_PUPDR_PULLUP(GPIOC_PIN1) | PIN_PUPDR_PULLUP(GPIOC_PIN2) | PIN_PUPDR_PULLUP(GPIOC_PIN3) | PIN_PUPDR_PULLUP(GPIOC_PIN4) | PIN_PUPDR_PULLUP(GPIOC_PIN5) | PIN_PUPDR_PULLUP(GPIOC_PIN6) | PIN_PUPDR_PULLUP(GPIOC_PIN7) | PIN_PUPDR_PULLUP(GPIOC_PIN8) | PIN_PUPDR_PULLUP(GPIOC_PIN9) | PIN_PUPDR_PULLUP(GPIOC_PIN10) | PIN_PUPDR_PULLUP(GPIOC_PIN11) | PIN_PUPDR_PULLUP(GPIOC_PIN12) | PIN_PUPDR_PULLUP(GPIOC_PIN13) | PIN_PUPDR_FLOATING(GPIOC_PIN14) | PIN_PUPDR_FLOATING(GPIOC_PIN15))
306#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | PIN_ODR_HIGH(GPIOC_PIN1) | PIN_ODR_HIGH(GPIOC_PIN2) | PIN_ODR_HIGH(GPIOC_PIN3) | PIN_ODR_HIGH(GPIOC_PIN4) | PIN_ODR_HIGH(GPIOC_PIN5) | PIN_ODR_HIGH(GPIOC_PIN6) | PIN_ODR_HIGH(GPIOC_PIN7) | PIN_ODR_HIGH(GPIOC_PIN8) | PIN_ODR_HIGH(GPIOC_PIN9) | PIN_ODR_HIGH(GPIOC_PIN10) | PIN_ODR_HIGH(GPIOC_PIN11) | PIN_ODR_HIGH(GPIOC_PIN12) | PIN_ODR_HIGH(GPIOC_PIN13) | PIN_ODR_HIGH(GPIOC_PIN14) | PIN_ODR_HIGH(GPIOC_PIN15))
307#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | PIN_AFIO_AF(GPIOC_PIN1, 0) | PIN_AFIO_AF(GPIOC_PIN2, 0) | PIN_AFIO_AF(GPIOC_PIN3, 0) | PIN_AFIO_AF(GPIOC_PIN4, 0) | PIN_AFIO_AF(GPIOC_PIN5, 0) | PIN_AFIO_AF(GPIOC_PIN6, 0) | PIN_AFIO_AF(GPIOC_PIN7, 0))
308#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | PIN_AFIO_AF(GPIOC_PIN9, 0) | PIN_AFIO_AF(GPIOC_PIN10, 0) | PIN_AFIO_AF(GPIOC_PIN11, 0) | PIN_AFIO_AF(GPIOC_PIN12, 0) | PIN_AFIO_AF(GPIOC_PIN13, 0) | PIN_AFIO_AF(GPIOC_PIN14, 0) | PIN_AFIO_AF(GPIOC_PIN15, 0))
309
310/*
311 * GPIOD setup:
312 *
313 * PD0 - PIN0 (input pullup).
314 * PD1 - PIN1 (input pullup).
315 * PD2 - PIN2 (input pullup).
316 * PD3 - PIN3 (input pullup).
317 * PD4 - PIN4 (input pullup).
318 * PD5 - PIN5 (input pullup).
319 * PD6 - PIN6 (input pullup).
320 * PD7 - PIN7 (input pullup).
321 * PD8 - PIN8 (input pullup).
322 * PD9 - PIN9 (input pullup).
323 * PD11 - PIN10 (input pullup).
324 * PD11 - PIN11 (input pullup).
325 * PD12 - PIN12 (input pullup).
326 * PD13 - PIN13 (input pullup).
327 * PD14 - PIN14 (input pullup).
328 * PD15 - PIN15 (input pullup).
329 */
330#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | PIN_MODE_INPUT(GPIOD_PIN1) | PIN_MODE_INPUT(GPIOD_PIN2) | PIN_MODE_INPUT(GPIOD_PIN3) | PIN_MODE_INPUT(GPIOD_PIN4) | PIN_MODE_INPUT(GPIOD_PIN5) | PIN_MODE_INPUT(GPIOD_PIN6) | PIN_MODE_INPUT(GPIOD_PIN7) | PIN_MODE_INPUT(GPIOD_PIN8) | PIN_MODE_INPUT(GPIOD_PIN9) | PIN_MODE_INPUT(GPIOD_PIN10) | PIN_MODE_INPUT(GPIOD_PIN11) | PIN_MODE_INPUT(GPIOD_PIN12) | PIN_MODE_INPUT(GPIOD_PIN13) | PIN_MODE_INPUT(GPIOD_PIN14) | PIN_MODE_INPUT(GPIOD_PIN15))
331#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
332#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | PIN_OSPEED_VERYLOW(GPIOD_PIN1) | PIN_OSPEED_VERYLOW(GPIOD_PIN2) | PIN_OSPEED_VERYLOW(GPIOD_PIN3) | PIN_OSPEED_VERYLOW(GPIOD_PIN4) | PIN_OSPEED_VERYLOW(GPIOD_PIN5) | PIN_OSPEED_VERYLOW(GPIOD_PIN6) | PIN_OSPEED_VERYLOW(GPIOD_PIN7) | PIN_OSPEED_VERYLOW(GPIOD_PIN8) | PIN_OSPEED_VERYLOW(GPIOD_PIN9) | PIN_OSPEED_VERYLOW(GPIOD_PIN10) | PIN_OSPEED_VERYLOW(GPIOD_PIN11) | PIN_OSPEED_VERYLOW(GPIOD_PIN12) | PIN_OSPEED_VERYLOW(GPIOD_PIN13) | PIN_OSPEED_VERYLOW(GPIOD_PIN14) | PIN_OSPEED_VERYLOW(GPIOD_PIN15))
333#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | PIN_PUPDR_PULLUP(GPIOD_PIN1) | PIN_PUPDR_PULLUP(GPIOD_PIN2) | PIN_PUPDR_PULLUP(GPIOD_PIN3) | PIN_PUPDR_PULLUP(GPIOD_PIN4) | PIN_PUPDR_PULLUP(GPIOD_PIN5) | PIN_PUPDR_PULLUP(GPIOD_PIN6) | PIN_PUPDR_PULLUP(GPIOD_PIN7) | PIN_PUPDR_PULLUP(GPIOD_PIN8) | PIN_PUPDR_PULLUP(GPIOD_PIN9) | PIN_PUPDR_PULLUP(GPIOD_PIN10) | PIN_PUPDR_PULLUP(GPIOD_PIN11) | PIN_PUPDR_PULLUP(GPIOD_PIN12) | PIN_PUPDR_PULLUP(GPIOD_PIN13) | PIN_PUPDR_PULLUP(GPIOD_PIN14) | PIN_PUPDR_PULLUP(GPIOD_PIN15))
334#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | PIN_ODR_HIGH(GPIOD_PIN1) | PIN_ODR_HIGH(GPIOD_PIN2) | PIN_ODR_HIGH(GPIOD_PIN3) | PIN_ODR_HIGH(GPIOD_PIN4) | PIN_ODR_HIGH(GPIOD_PIN5) | PIN_ODR_HIGH(GPIOD_PIN6) | PIN_ODR_HIGH(GPIOD_PIN7) | PIN_ODR_HIGH(GPIOD_PIN8) | PIN_ODR_HIGH(GPIOD_PIN9) | PIN_ODR_HIGH(GPIOD_PIN10) | PIN_ODR_HIGH(GPIOD_PIN11) | PIN_ODR_HIGH(GPIOD_PIN12) | PIN_ODR_HIGH(GPIOD_PIN13) | PIN_ODR_HIGH(GPIOD_PIN14) | PIN_ODR_HIGH(GPIOD_PIN15))
335#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | PIN_AFIO_AF(GPIOD_PIN1, 0) | PIN_AFIO_AF(GPIOD_PIN2, 0) | PIN_AFIO_AF(GPIOD_PIN3, 0) | PIN_AFIO_AF(GPIOD_PIN4, 0) | PIN_AFIO_AF(GPIOD_PIN5, 0) | PIN_AFIO_AF(GPIOD_PIN6, 0) | PIN_AFIO_AF(GPIOD_PIN7, 0))
336#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | PIN_AFIO_AF(GPIOD_PIN9, 0) | PIN_AFIO_AF(GPIOD_PIN10, 0) | PIN_AFIO_AF(GPIOD_PIN11, 0) | PIN_AFIO_AF(GPIOD_PIN12, 0) | PIN_AFIO_AF(GPIOD_PIN13, 0) | PIN_AFIO_AF(GPIOD_PIN14, 0) | PIN_AFIO_AF(GPIOD_PIN15, 0))
337
338/*
339 * GPIOE setup:
340 *
341 * PE0 - PIN0 (input pullup).
342 * PE1 - PIN1 (input pullup).
343 * PE2 - PIN2 (input pullup).
344 * PE3 - PIN3 L3GD20_CS (output pushpull maximum).
345 * PE4 - PIN4 (input pullup).
346 * PE5 - PIN5 (input pullup).
347 * PE6 - PIN6 (input pullup).
348 * PE7 - PIN7 (input pullup).
349 * PE8 - PIN8 (output pushpull maximum).
350 * PE9 - PIN9 (output pushpull maximum).
351 * PE10 - PIN10 (output pushpull maximum).
352 * PE11 - PIN11 (output pushpull maximum).
353 * PE12 - PIN12 (output pushpull maximum).
354 * PE13 - PIN13 (output pushpull maximum).
355 * PE14 - PIN14 (output pushpull maximum).
356 * PE15 - PIN15 (output pushpull maximum).
357 */
358#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | PIN_MODE_INPUT(GPIOE_PIN1) | PIN_MODE_INPUT(GPIOE_PIN2) | PIN_MODE_OUTPUT(GPIOE_PIN3) | PIN_MODE_INPUT(GPIOE_PIN4) | PIN_MODE_INPUT(GPIOE_PIN5) | PIN_MODE_INPUT(GPIOE_PIN6) | PIN_MODE_INPUT(GPIOE_PIN7) | PIN_MODE_OUTPUT(GPIOE_PIN8) | PIN_MODE_OUTPUT(GPIOE_PIN9) | PIN_MODE_OUTPUT(GPIOE_PIN10) | PIN_MODE_OUTPUT(GPIOE_PIN11) | PIN_MODE_OUTPUT(GPIOE_PIN12) | PIN_MODE_OUTPUT(GPIOE_PIN13) | PIN_MODE_OUTPUT(GPIOE_PIN14) | PIN_MODE_OUTPUT(GPIOE_PIN15))
359#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
360#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | PIN_OSPEED_VERYLOW(GPIOE_PIN1) | PIN_OSPEED_VERYLOW(GPIOE_PIN2) | PIN_OSPEED_HIGH(GPIOE_PIN3) | PIN_OSPEED_VERYLOW(GPIOE_PIN4) | PIN_OSPEED_VERYLOW(GPIOE_PIN5) | PIN_OSPEED_VERYLOW(GPIOE_PIN6) | PIN_OSPEED_VERYLOW(GPIOE_PIN7) | PIN_OSPEED_HIGH(GPIOE_PIN8) | PIN_OSPEED_HIGH(GPIOE_PIN9) | PIN_OSPEED_HIGH(GPIOE_PIN10) | PIN_OSPEED_HIGH(GPIOE_PIN11) | PIN_OSPEED_HIGH(GPIOE_PIN12) | PIN_OSPEED_HIGH(GPIOE_PIN13) | PIN_OSPEED_HIGH(GPIOE_PIN14) | PIN_OSPEED_HIGH(GPIOE_PIN15))
361#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | PIN_PUPDR_PULLUP(GPIOE_PIN1) | PIN_PUPDR_PULLUP(GPIOE_PIN2) | PIN_PUPDR_FLOATING(GPIOE_PIN3) | PIN_PUPDR_PULLUP(GPIOE_PIN4) | PIN_PUPDR_PULLUP(GPIOE_PIN5) | PIN_PUPDR_PULLUP(GPIOE_PIN6) | PIN_PUPDR_PULLUP(GPIOE_PIN7) | PIN_PUPDR_PULLUP(GPIOE_PIN8) | PIN_PUPDR_PULLUP(GPIOE_PIN9) | PIN_PUPDR_PULLUP(GPIOE_PIN10) | PIN_PUPDR_FLOATING(GPIOE_PIN11) | PIN_PUPDR_PULLUP(GPIOE_PIN12) | PIN_PUPDR_FLOATING(GPIOE_PIN13) | PIN_PUPDR_FLOATING(GPIOE_PIN14) | PIN_PUPDR_FLOATING(GPIOE_PIN15))
362#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | PIN_ODR_HIGH(GPIOE_PIN1) | PIN_ODR_HIGH(GPIOE_PIN2) | PIN_ODR_HIGH(GPIOE_PIN3) | PIN_ODR_HIGH(GPIOE_PIN4) | PIN_ODR_HIGH(GPIOE_PIN5) | PIN_ODR_HIGH(GPIOE_PIN6) | PIN_ODR_HIGH(GPIOE_PIN7) | PIN_ODR_LOW(GPIOE_PIN8) | PIN_ODR_LOW(GPIOE_PIN9) | PIN_ODR_LOW(GPIOE_PIN10) | PIN_ODR_LOW(GPIOE_PIN11) | PIN_ODR_LOW(GPIOE_PIN12) | PIN_ODR_LOW(GPIOE_PIN13) | PIN_ODR_LOW(GPIOE_PIN14) | PIN_ODR_LOW(GPIOE_PIN15))
363#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | PIN_AFIO_AF(GPIOE_PIN1, 0) | PIN_AFIO_AF(GPIOE_PIN2, 0) | PIN_AFIO_AF(GPIOE_PIN3, 0) | PIN_AFIO_AF(GPIOE_PIN4, 0) | PIN_AFIO_AF(GPIOE_PIN5, 0) | PIN_AFIO_AF(GPIOE_PIN6, 0) | PIN_AFIO_AF(GPIOE_PIN7, 0))
364#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | PIN_AFIO_AF(GPIOE_PIN9, 0) | PIN_AFIO_AF(GPIOE_PIN10, 0) | PIN_AFIO_AF(GPIOE_PIN11, 0) | PIN_AFIO_AF(GPIOE_PIN12, 0) | PIN_AFIO_AF(GPIOE_PIN13, 0) | PIN_AFIO_AF(GPIOE_PIN14, 0) | PIN_AFIO_AF(GPIOE_PIN15, 0))
365
366/*
367 * GPIOF setup:
368 *
369 * PF0 - I2C2_SDA (input floating).
370 * PF1 - I2C2_SCL (input floating).
371 * PF2 - PIN2 (input pullup).
372 * PF3 - PIN3 (input pullup).
373 * PF4 - PIN4 (input pullup).
374 * PF5 - PIN5 (input pullup).
375 * PF6 - PIN6 (input pullup).
376 * PF7 - PIN7 (input pullup).
377 * PF8 - PIN8 (input pullup).
378 * PF9 - PIN9 (input pullup).
379 * PF10 - PIN10 (input pullup).
380 * PF11 - PIN11 (input pullup).
381 * PF12 - PIN12 (input pullup).
382 * PF13 - PIN13 (input pullup).
383 * PF14 - PIN14 (input pullup).
384 * PF15 - PIN15 (input pullup).
385 */
386#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_I2C2_SDA) | PIN_MODE_INPUT(GPIOF_I2C2_SCL) | PIN_MODE_INPUT(GPIOF_PIN2) | PIN_MODE_INPUT(GPIOF_PIN3) | PIN_MODE_INPUT(GPIOF_PIN4) | PIN_MODE_INPUT(GPIOF_PIN5) | PIN_MODE_INPUT(GPIOF_PIN6) | PIN_MODE_INPUT(GPIOF_PIN7) | PIN_MODE_INPUT(GPIOF_PIN8) | PIN_MODE_INPUT(GPIOF_PIN9) | PIN_MODE_INPUT(GPIOF_PIN10) | PIN_MODE_INPUT(GPIOF_PIN11) | PIN_MODE_INPUT(GPIOF_PIN12) | PIN_MODE_INPUT(GPIOF_PIN13) | PIN_MODE_INPUT(GPIOF_PIN14) | PIN_MODE_INPUT(GPIOF_PIN15))
387#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_I2C2_SDA) | PIN_OTYPE_PUSHPULL(GPIOF_I2C2_SCL) | PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
388#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_I2C2_SDA) | PIN_OSPEED_HIGH(GPIOF_I2C2_SCL) | PIN_OSPEED_VERYLOW(GPIOF_PIN2) | PIN_OSPEED_VERYLOW(GPIOF_PIN3) | PIN_OSPEED_VERYLOW(GPIOF_PIN4) | PIN_OSPEED_VERYLOW(GPIOF_PIN5) | PIN_OSPEED_VERYLOW(GPIOF_PIN6) | PIN_OSPEED_VERYLOW(GPIOF_PIN7) | PIN_OSPEED_VERYLOW(GPIOF_PIN8) | PIN_OSPEED_VERYLOW(GPIOF_PIN9) | PIN_OSPEED_VERYLOW(GPIOF_PIN10) | PIN_OSPEED_VERYLOW(GPIOF_PIN11) | PIN_OSPEED_VERYLOW(GPIOF_PIN12) | PIN_OSPEED_VERYLOW(GPIOF_PIN13) | PIN_OSPEED_VERYLOW(GPIOF_PIN14) | PIN_OSPEED_VERYLOW(GPIOF_PIN15))
389#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_I2C2_SDA) | PIN_PUPDR_FLOATING(GPIOF_I2C2_SCL) | PIN_PUPDR_PULLUP(GPIOF_PIN2) | PIN_PUPDR_PULLUP(GPIOF_PIN3) | PIN_PUPDR_PULLUP(GPIOF_PIN4) | PIN_PUPDR_PULLUP(GPIOF_PIN5) | PIN_PUPDR_PULLUP(GPIOF_PIN6) | PIN_PUPDR_PULLUP(GPIOF_PIN7) | PIN_PUPDR_PULLUP(GPIOF_PIN8) | PIN_PUPDR_PULLUP(GPIOF_PIN9) | PIN_PUPDR_PULLUP(GPIOF_PIN10) | PIN_PUPDR_PULLUP(GPIOF_PIN11) | PIN_PUPDR_PULLUP(GPIOF_PIN12) | PIN_PUPDR_PULLUP(GPIOF_PIN13) | PIN_PUPDR_PULLUP(GPIOF_PIN14) | PIN_PUPDR_PULLUP(GPIOF_PIN15))
390#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_I2C2_SDA) | PIN_ODR_HIGH(GPIOF_I2C2_SCL) | PIN_ODR_HIGH(GPIOF_PIN2) | PIN_ODR_HIGH(GPIOF_PIN3) | PIN_ODR_HIGH(GPIOF_PIN4) | PIN_ODR_HIGH(GPIOF_PIN5) | PIN_ODR_HIGH(GPIOF_PIN6) | PIN_ODR_HIGH(GPIOF_PIN7) | PIN_ODR_HIGH(GPIOF_PIN8) | PIN_ODR_HIGH(GPIOF_PIN9) | PIN_ODR_HIGH(GPIOF_PIN10) | PIN_ODR_HIGH(GPIOF_PIN11) | PIN_ODR_HIGH(GPIOF_PIN12) | PIN_ODR_HIGH(GPIOF_PIN13) | PIN_ODR_HIGH(GPIOF_PIN14) | PIN_ODR_HIGH(GPIOF_PIN15))
391#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_I2C2_SDA, 0) | PIN_AFIO_AF(GPIOF_I2C2_SCL, 0) | PIN_AFIO_AF(GPIOF_PIN2, 0) | PIN_AFIO_AF(GPIOF_PIN3, 0) | PIN_AFIO_AF(GPIOF_PIN4, 0) | PIN_AFIO_AF(GPIOF_PIN5, 0) | PIN_AFIO_AF(GPIOF_PIN6, 0) | PIN_AFIO_AF(GPIOF_PIN7, 0))
392#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | PIN_AFIO_AF(GPIOF_PIN9, 0) | PIN_AFIO_AF(GPIOF_PIN10, 0) | PIN_AFIO_AF(GPIOF_PIN11, 0) | PIN_AFIO_AF(GPIOF_PIN12, 0) | PIN_AFIO_AF(GPIOF_PIN13, 0) | PIN_AFIO_AF(GPIOF_PIN14, 0) | PIN_AFIO_AF(GPIOF_PIN15, 0))
393
394/*
395 * GPIOG setup:
396 *
397 * PG0 - PIN0 (input pullup).
398 * PG1 - PIN1 (input pullup).
399 * PG2 - PIN2 (input pullup).
400 * PG3 - PIN3 (input pullup).
401 * PG4 - PIN4 (input pullup).
402 * PG5 - PIN5 (input pullup).
403 * PG6 - PIN6 (input pullup).
404 * PG7 - PIN7 (input pullup).
405 * PG8 - PIN8 (input pullup).
406 * PG9 - PIN9 (input pullup).
407 * PG10 - PIN10 (input pullup).
408 * PG11 - PIN11 (input pullup).
409 * PG12 - PIN12 (input pullup).
410 * PG13 - PIN13 (input pullup).
411 * PG14 - PIN14 (input pullup).
412 * PG15 - PIN15 (input pullup).
413 */
414#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | PIN_MODE_INPUT(GPIOG_PIN1) | PIN_MODE_INPUT(GPIOG_PIN2) | PIN_MODE_INPUT(GPIOG_PIN3) | PIN_MODE_INPUT(GPIOG_PIN4) | PIN_MODE_INPUT(GPIOG_PIN5) | PIN_MODE_INPUT(GPIOG_PIN6) | PIN_MODE_INPUT(GPIOG_PIN7) | PIN_MODE_INPUT(GPIOG_PIN8) | PIN_MODE_INPUT(GPIOG_PIN9) | PIN_MODE_INPUT(GPIOG_PIN10) | PIN_MODE_INPUT(GPIOG_PIN11) | PIN_MODE_INPUT(GPIOG_PIN12) | PIN_MODE_INPUT(GPIOG_PIN13) | PIN_MODE_INPUT(GPIOG_PIN14) | PIN_MODE_INPUT(GPIOG_PIN15))
415#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
416#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | PIN_OSPEED_VERYLOW(GPIOG_PIN1) | PIN_OSPEED_VERYLOW(GPIOG_PIN2) | PIN_OSPEED_VERYLOW(GPIOG_PIN3) | PIN_OSPEED_VERYLOW(GPIOG_PIN4) | PIN_OSPEED_VERYLOW(GPIOG_PIN5) | PIN_OSPEED_VERYLOW(GPIOG_PIN6) | PIN_OSPEED_VERYLOW(GPIOG_PIN7) | PIN_OSPEED_VERYLOW(GPIOG_PIN8) | PIN_OSPEED_VERYLOW(GPIOG_PIN9) | PIN_OSPEED_VERYLOW(GPIOG_PIN10) | PIN_OSPEED_VERYLOW(GPIOG_PIN11) | PIN_OSPEED_VERYLOW(GPIOG_PIN12) | PIN_OSPEED_VERYLOW(GPIOG_PIN13) | PIN_OSPEED_VERYLOW(GPIOG_PIN14) | PIN_OSPEED_VERYLOW(GPIOG_PIN15))
417#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | PIN_PUPDR_PULLUP(GPIOG_PIN1) | PIN_PUPDR_PULLUP(GPIOG_PIN2) | PIN_PUPDR_PULLUP(GPIOG_PIN3) | PIN_PUPDR_PULLUP(GPIOG_PIN4) | PIN_PUPDR_PULLUP(GPIOG_PIN5) | PIN_PUPDR_PULLUP(GPIOG_PIN6) | PIN_PUPDR_PULLUP(GPIOG_PIN7) | PIN_PUPDR_PULLUP(GPIOG_PIN8) | PIN_PUPDR_PULLUP(GPIOG_PIN9) | PIN_PUPDR_PULLUP(GPIOG_PIN10) | PIN_PUPDR_PULLUP(GPIOG_PIN11) | PIN_PUPDR_PULLUP(GPIOG_PIN12) | PIN_PUPDR_PULLUP(GPIOG_PIN13) | PIN_PUPDR_PULLUP(GPIOG_PIN14) | PIN_PUPDR_PULLUP(GPIOG_PIN15))
418#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | PIN_ODR_HIGH(GPIOG_PIN1) | PIN_ODR_HIGH(GPIOG_PIN2) | PIN_ODR_HIGH(GPIOG_PIN3) | PIN_ODR_HIGH(GPIOG_PIN4) | PIN_ODR_HIGH(GPIOG_PIN5) | PIN_ODR_HIGH(GPIOG_PIN6) | PIN_ODR_HIGH(GPIOG_PIN7) | PIN_ODR_HIGH(GPIOG_PIN8) | PIN_ODR_HIGH(GPIOG_PIN9) | PIN_ODR_HIGH(GPIOG_PIN10) | PIN_ODR_HIGH(GPIOG_PIN11) | PIN_ODR_HIGH(GPIOG_PIN12) | PIN_ODR_HIGH(GPIOG_PIN13) | PIN_ODR_HIGH(GPIOG_PIN14) | PIN_ODR_HIGH(GPIOG_PIN15))
419#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | PIN_AFIO_AF(GPIOG_PIN1, 0) | PIN_AFIO_AF(GPIOG_PIN2, 0) | PIN_AFIO_AF(GPIOG_PIN3, 0) | PIN_AFIO_AF(GPIOG_PIN4, 0) | PIN_AFIO_AF(GPIOG_PIN5, 0) | PIN_AFIO_AF(GPIOG_PIN6, 0) | PIN_AFIO_AF(GPIOG_PIN7, 0))
420#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | PIN_AFIO_AF(GPIOG_PIN9, 0) | PIN_AFIO_AF(GPIOG_PIN10, 0) | PIN_AFIO_AF(GPIOG_PIN11, 0) | PIN_AFIO_AF(GPIOG_PIN12, 0) | PIN_AFIO_AF(GPIOG_PIN13, 0) | PIN_AFIO_AF(GPIOG_PIN14, 0) | PIN_AFIO_AF(GPIOG_PIN15, 0))
421
422/*
423 * GPIOH setup:
424 *
425 * PH0 - PIN0 (input pullup).
426 * PH1 - PIN1 (input pullup).
427 * PH2 - PIN2 (input pullup).
428 * PH3 - PIN3 (input pullup).
429 * PH4 - PIN4 (input pullup).
430 * PH5 - PIN5 (input pullup).
431 * PH6 - PIN6 (input pullup).
432 * PH7 - PIN7 (input pullup).
433 * PH8 - PIN8 (input pullup).
434 * PH9 - PIN9 (input pullup).
435 * PH10 - PIN10 (input pullup).
436 * PH11 - PIN11 (input pullup).
437 * PH12 - PIN12 (input pullup).
438 * PH13 - PIN13 (input pullup).
439 * PH14 - PIN14 (input pullup).
440 * PH15 - PIN15 (input pullup).
441 */
442#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | PIN_MODE_INPUT(GPIOH_PIN1) | PIN_MODE_INPUT(GPIOH_PIN2) | PIN_MODE_INPUT(GPIOH_PIN3) | PIN_MODE_INPUT(GPIOH_PIN4) | PIN_MODE_INPUT(GPIOH_PIN5) | PIN_MODE_INPUT(GPIOH_PIN6) | PIN_MODE_INPUT(GPIOH_PIN7) | PIN_MODE_INPUT(GPIOH_PIN8) | PIN_MODE_INPUT(GPIOH_PIN9) | PIN_MODE_INPUT(GPIOH_PIN10) | PIN_MODE_INPUT(GPIOH_PIN11) | PIN_MODE_INPUT(GPIOH_PIN12) | PIN_MODE_INPUT(GPIOH_PIN13) | PIN_MODE_INPUT(GPIOH_PIN14) | PIN_MODE_INPUT(GPIOH_PIN15))
443#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
444#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOH_PIN0) | PIN_OSPEED_VERYLOW(GPIOH_PIN1) | PIN_OSPEED_VERYLOW(GPIOH_PIN2) | PIN_OSPEED_VERYLOW(GPIOH_PIN3) | PIN_OSPEED_VERYLOW(GPIOH_PIN4) | PIN_OSPEED_VERYLOW(GPIOH_PIN5) | PIN_OSPEED_VERYLOW(GPIOH_PIN6) | PIN_OSPEED_VERYLOW(GPIOH_PIN7) | PIN_OSPEED_VERYLOW(GPIOH_PIN8) | PIN_OSPEED_VERYLOW(GPIOH_PIN9) | PIN_OSPEED_VERYLOW(GPIOH_PIN10) | PIN_OSPEED_VERYLOW(GPIOH_PIN11) | PIN_OSPEED_VERYLOW(GPIOH_PIN12) | PIN_OSPEED_VERYLOW(GPIOH_PIN13) | PIN_OSPEED_VERYLOW(GPIOH_PIN14) | PIN_OSPEED_VERYLOW(GPIOH_PIN15))
445#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLUP(GPIOH_PIN0) | PIN_PUPDR_PULLUP(GPIOH_PIN1) | PIN_PUPDR_PULLUP(GPIOH_PIN2) | PIN_PUPDR_PULLUP(GPIOH_PIN3) | PIN_PUPDR_PULLUP(GPIOH_PIN4) | PIN_PUPDR_PULLUP(GPIOH_PIN5) | PIN_PUPDR_PULLUP(GPIOH_PIN6) | PIN_PUPDR_PULLUP(GPIOH_PIN7) | PIN_PUPDR_PULLUP(GPIOH_PIN8) | PIN_PUPDR_PULLUP(GPIOH_PIN9) | PIN_PUPDR_PULLUP(GPIOH_PIN10) | PIN_PUPDR_PULLUP(GPIOH_PIN11) | PIN_PUPDR_PULLUP(GPIOH_PIN12) | PIN_PUPDR_PULLUP(GPIOH_PIN13) | PIN_PUPDR_PULLUP(GPIOH_PIN14) | PIN_PUPDR_PULLUP(GPIOH_PIN15))
446#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | PIN_ODR_HIGH(GPIOH_PIN1) | PIN_ODR_HIGH(GPIOH_PIN2) | PIN_ODR_HIGH(GPIOH_PIN3) | PIN_ODR_HIGH(GPIOH_PIN4) | PIN_ODR_HIGH(GPIOH_PIN5) | PIN_ODR_HIGH(GPIOH_PIN6) | PIN_ODR_HIGH(GPIOH_PIN7) | PIN_ODR_HIGH(GPIOH_PIN8) | PIN_ODR_HIGH(GPIOH_PIN9) | PIN_ODR_HIGH(GPIOH_PIN10) | PIN_ODR_HIGH(GPIOH_PIN11) | PIN_ODR_HIGH(GPIOH_PIN12) | PIN_ODR_HIGH(GPIOH_PIN13) | PIN_ODR_HIGH(GPIOH_PIN14) | PIN_ODR_HIGH(GPIOH_PIN15))
447#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | PIN_AFIO_AF(GPIOH_PIN1, 0) | PIN_AFIO_AF(GPIOH_PIN2, 0) | PIN_AFIO_AF(GPIOH_PIN3, 0) | PIN_AFIO_AF(GPIOH_PIN4, 0) | PIN_AFIO_AF(GPIOH_PIN5, 0) | PIN_AFIO_AF(GPIOH_PIN6, 0) | PIN_AFIO_AF(GPIOH_PIN7, 0))
448#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | PIN_AFIO_AF(GPIOH_PIN9, 0) | PIN_AFIO_AF(GPIOH_PIN10, 0) | PIN_AFIO_AF(GPIOH_PIN11, 0) | PIN_AFIO_AF(GPIOH_PIN12, 0) | PIN_AFIO_AF(GPIOH_PIN13, 0) | PIN_AFIO_AF(GPIOH_PIN14, 0) | PIN_AFIO_AF(GPIOH_PIN15, 0))
449
450/*
451 * USB bus activation macro, required by the USB driver.
452 */
453// #define usb_lld_connect_bus(usbp)
454#define usb_lld_connect_bus(usbp) (palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_ALTERNATE(14)))
455// #define usb_lld_connect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_INPUT)
456/*
457 * USB bus de-activation macro, required by the USB driver.
458 */
459// #define usb_lld_disconnect_bus(usbp)
460#define usb_lld_disconnect_bus(usbp) \
461 (palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_OUTPUT_PUSHPULL)); \
462 palClearPad(GPIOA, GPIOA_USB_DP)
463// #define usb_lld_disconnect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_OUTPUT_PUSHPULL); palClearPad(GPIOA, 12)
464
465#if !defined(_FROM_ASM_)
466# ifdef __cplusplus
467extern "C" {
468# endif
469void boardInit(void);
470# ifdef __cplusplus
471}
472# endif
473#endif /* _FROM_ASM_ */
474
475#endif /* _BOARD_H_ */
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk b/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk
new file mode 100644
index 000000000..842e33590
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk
@@ -0,0 +1,9 @@
1# List of all the board related files.
2BOARDSRC = $(BOARD_PATH)/board/board.c
3
4# Required include directories
5BOARDINC = $(BOARD_PATH)/board
6
7# Shared variables
8ALLCSRC += $(BOARDSRC)
9ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h
new file mode 100644
index 000000000..3b0e9d20a
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h
@@ -0,0 +1,7 @@
1/* Address for jumping to bootloader on STM32 chips. */
2/* It is chip dependent, the correct number can be looked up here:
3 * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
4 * This also requires a patch to chibios:
5 * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
6 */
7#define STM32_BOOTLOADER_ADDRESS 0x1FFFD800
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h
new file mode 100644
index 000000000..aac330370
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h
@@ -0,0 +1,714 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file rt/templates/chconf.h
19 * @brief Configuration file template.
20 * @details A copy of this file must be placed in each project directory, it
21 * contains the application specific kernel settings.
22 *
23 * @addtogroup config
24 * @details Kernel related settings and hooks.
25 * @{
26 */
27
28#ifndef CHCONF_H
29#define CHCONF_H
30
31#define _CHIBIOS_RT_CONF_
32#define _CHIBIOS_RT_CONF_VER_6_0_
33
34/*===========================================================================*/
35/**
36 * @name System timers settings
37 * @{
38 */
39/*===========================================================================*/
40
41/**
42 * @brief System time counter resolution.
43 * @note Allowed values are 16 or 32 bits.
44 */
45#if !defined(CH_CFG_ST_RESOLUTION)
46#define CH_CFG_ST_RESOLUTION 32
47#endif
48
49/**
50 * @brief System tick frequency.
51 * @details Frequency of the system timer that drives the system ticks. This
52 * setting also defines the system tick time unit.
53 */
54#if !defined(CH_CFG_ST_FREQUENCY)
55#define CH_CFG_ST_FREQUENCY 100000
56#endif
57
58/**
59 * @brief Time intervals data size.
60 * @note Allowed values are 16, 32 or 64 bits.
61 */
62#if !defined(CH_CFG_INTERVALS_SIZE)
63#define CH_CFG_INTERVALS_SIZE 32
64#endif
65
66/**
67 * @brief Time types data size.
68 * @note Allowed values are 16 or 32 bits.
69 */
70#if !defined(CH_CFG_TIME_TYPES_SIZE)
71#define CH_CFG_TIME_TYPES_SIZE 32
72#endif
73
74/**
75 * @brief Time delta constant for the tick-less mode.
76 * @note If this value is zero then the system uses the classic
77 * periodic tick. This value represents the minimum number
78 * of ticks that is safe to specify in a timeout directive.
79 * The value one is not valid, timeouts are rounded up to
80 * this value.
81 */
82#if !defined(CH_CFG_ST_TIMEDELTA)
83#define CH_CFG_ST_TIMEDELTA 2
84#endif
85
86/** @} */
87
88/*===========================================================================*/
89/**
90 * @name Kernel parameters and options
91 * @{
92 */
93/*===========================================================================*/
94
95/**
96 * @brief Round robin interval.
97 * @details This constant is the number of system ticks allowed for the
98 * threads before preemption occurs. Setting this value to zero
99 * disables the preemption for threads with equal priority and the
100 * round robin becomes cooperative. Note that higher priority
101 * threads can still preempt, the kernel is always preemptive.
102 * @note Disabling the round robin preemption makes the kernel more compact
103 * and generally faster.
104 * @note The round robin preemption is not supported in tickless mode and
105 * must be set to zero in that case.
106 */
107#if !defined(CH_CFG_TIME_QUANTUM)
108#define CH_CFG_TIME_QUANTUM 0
109#endif
110
111/**
112 * @brief Managed RAM size.
113 * @details Size of the RAM area to be managed by the OS. If set to zero
114 * then the whole available RAM is used. The core memory is made
115 * available to the heap allocator and/or can be used directly through
116 * the simplified core memory allocator.
117 *
118 * @note In order to let the OS manage the whole RAM the linker script must
119 * provide the @p __heap_base__ and @p __heap_end__ symbols.
120 * @note Requires @p CH_CFG_USE_MEMCORE.
121 */
122#if !defined(CH_CFG_MEMCORE_SIZE)
123#define CH_CFG_MEMCORE_SIZE 0
124#endif
125
126/**
127 * @brief Idle thread automatic spawn suppression.
128 * @details When this option is activated the function @p chSysInit()
129 * does not spawn the idle thread. The application @p main()
130 * function becomes the idle thread and must implement an
131 * infinite loop.
132 */
133#if !defined(CH_CFG_NO_IDLE_THREAD)
134#define CH_CFG_NO_IDLE_THREAD FALSE
135#endif
136
137/** @} */
138
139/*===========================================================================*/
140/**
141 * @name Performance options
142 * @{
143 */
144/*===========================================================================*/
145
146/**
147 * @brief OS optimization.
148 * @details If enabled then time efficient rather than space efficient code
149 * is used when two possible implementations exist.
150 *
151 * @note This is not related to the compiler optimization options.
152 * @note The default is @p TRUE.
153 */
154#if !defined(CH_CFG_OPTIMIZE_SPEED)
155#define CH_CFG_OPTIMIZE_SPEED TRUE
156#endif
157
158/** @} */
159
160/*===========================================================================*/
161/**
162 * @name Subsystem options
163 * @{
164 */
165/*===========================================================================*/
166
167/**
168 * @brief Time Measurement APIs.
169 * @details If enabled then the time measurement APIs are included in
170 * the kernel.
171 *
172 * @note The default is @p TRUE.
173 */
174#if !defined(CH_CFG_USE_TM)
175#define CH_CFG_USE_TM TRUE
176#endif
177
178/**
179 * @brief Threads registry APIs.
180 * @details If enabled then the registry APIs are included in the kernel.
181 *
182 * @note The default is @p TRUE.
183 */
184#if !defined(CH_CFG_USE_REGISTRY)
185#define CH_CFG_USE_REGISTRY TRUE
186#endif
187
188/**
189 * @brief Threads synchronization APIs.
190 * @details If enabled then the @p chThdWait() function is included in
191 * the kernel.
192 *
193 * @note The default is @p TRUE.
194 */
195#if !defined(CH_CFG_USE_WAITEXIT)
196#define CH_CFG_USE_WAITEXIT TRUE
197#endif
198
199/**
200 * @brief Semaphores APIs.
201 * @details If enabled then the Semaphores APIs are included in the kernel.
202 *
203 * @note The default is @p TRUE.
204 */
205#if !defined(CH_CFG_USE_SEMAPHORES)
206#define CH_CFG_USE_SEMAPHORES TRUE
207#endif
208
209/**
210 * @brief Semaphores queuing mode.
211 * @details If enabled then the threads are enqueued on semaphores by
212 * priority rather than in FIFO order.
213 *
214 * @note The default is @p FALSE. Enable this if you have special
215 * requirements.
216 * @note Requires @p CH_CFG_USE_SEMAPHORES.
217 */
218#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
219#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
220#endif
221
222/**
223 * @brief Mutexes APIs.
224 * @details If enabled then the mutexes APIs are included in the kernel.
225 *
226 * @note The default is @p TRUE.
227 */
228#if !defined(CH_CFG_USE_MUTEXES)
229#define CH_CFG_USE_MUTEXES TRUE
230#endif
231
232/**
233 * @brief Enables recursive behavior on mutexes.
234 * @note Recursive mutexes are heavier and have an increased
235 * memory footprint.
236 *
237 * @note The default is @p FALSE.
238 * @note Requires @p CH_CFG_USE_MUTEXES.
239 */
240#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
241#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
242#endif
243
244/**
245 * @brief Conditional Variables APIs.
246 * @details If enabled then the conditional variables APIs are included
247 * in the kernel.
248 *
249 * @note The default is @p TRUE.
250 * @note Requires @p CH_CFG_USE_MUTEXES.
251 */
252#if !defined(CH_CFG_USE_CONDVARS)
253#define CH_CFG_USE_CONDVARS TRUE
254#endif
255
256/**
257 * @brief Conditional Variables APIs with timeout.
258 * @details If enabled then the conditional variables APIs with timeout
259 * specification are included in the kernel.
260 *
261 * @note The default is @p TRUE.
262 * @note Requires @p CH_CFG_USE_CONDVARS.
263 */
264#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
265#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
266#endif
267
268/**
269 * @brief Events Flags APIs.
270 * @details If enabled then the event flags APIs are included in the kernel.
271 *
272 * @note The default is @p TRUE.
273 */
274#if !defined(CH_CFG_USE_EVENTS)
275#define CH_CFG_USE_EVENTS TRUE
276#endif
277
278/**
279 * @brief Events Flags APIs with timeout.
280 * @details If enabled then the events APIs with timeout specification
281 * are included in the kernel.
282 *
283 * @note The default is @p TRUE.
284 * @note Requires @p CH_CFG_USE_EVENTS.
285 */
286#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
287#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
288#endif
289
290/**
291 * @brief Synchronous Messages APIs.
292 * @details If enabled then the synchronous messages APIs are included
293 * in the kernel.
294 *
295 * @note The default is @p TRUE.
296 */
297#if !defined(CH_CFG_USE_MESSAGES)
298#define CH_CFG_USE_MESSAGES TRUE
299#endif
300
301/**
302 * @brief Synchronous Messages queuing mode.
303 * @details If enabled then messages are served by priority rather than in
304 * FIFO order.
305 *
306 * @note The default is @p FALSE. Enable this if you have special
307 * requirements.
308 * @note Requires @p CH_CFG_USE_MESSAGES.
309 */
310#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
311#define CH_CFG_USE_MESSAGES_PRIORITY TRUE
312#endif
313
314/**
315 * @brief Mailboxes APIs.
316 * @details If enabled then the asynchronous messages (mailboxes) APIs are
317 * included in the kernel.
318 *
319 * @note The default is @p TRUE.
320 * @note Requires @p CH_CFG_USE_SEMAPHORES.
321 */
322#if !defined(CH_CFG_USE_MAILBOXES)
323#define CH_CFG_USE_MAILBOXES TRUE
324#endif
325
326/**
327 * @brief Core Memory Manager APIs.
328 * @details If enabled then the core memory manager APIs are included
329 * in the kernel.
330 *
331 * @note The default is @p TRUE.
332 */
333#if !defined(CH_CFG_USE_MEMCORE)
334#define CH_CFG_USE_MEMCORE TRUE
335#endif
336
337/**
338 * @brief Heap Allocator APIs.
339 * @details If enabled then the memory heap allocator APIs are included
340 * in the kernel.
341 *
342 * @note The default is @p TRUE.
343 * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
344 * @p CH_CFG_USE_SEMAPHORES.
345 * @note Mutexes are recommended.
346 */
347#if !defined(CH_CFG_USE_HEAP)
348#define CH_CFG_USE_HEAP TRUE
349#endif
350
351/**
352 * @brief Memory Pools Allocator APIs.
353 * @details If enabled then the memory pools allocator APIs are included
354 * in the kernel.
355 *
356 * @note The default is @p TRUE.
357 */
358#if !defined(CH_CFG_USE_MEMPOOLS)
359#define CH_CFG_USE_MEMPOOLS TRUE
360#endif
361
362/**
363 * @brief Objects FIFOs APIs.
364 * @details If enabled then the objects FIFOs APIs are included
365 * in the kernel.
366 *
367 * @note The default is @p TRUE.
368 */
369#if !defined(CH_CFG_USE_OBJ_FIFOS)
370#define CH_CFG_USE_OBJ_FIFOS TRUE
371#endif
372
373/**
374 * @brief Pipes APIs.
375 * @details If enabled then the pipes APIs are included
376 * in the kernel.
377 *
378 * @note The default is @p TRUE.
379 */
380#if !defined(CH_CFG_USE_PIPES)
381#define CH_CFG_USE_PIPES TRUE
382#endif
383
384/**
385 * @brief Dynamic Threads APIs.
386 * @details If enabled then the dynamic threads creation APIs are included
387 * in the kernel.
388 *
389 * @note The default is @p TRUE.
390 * @note Requires @p CH_CFG_USE_WAITEXIT.
391 * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
392 */
393#if !defined(CH_CFG_USE_DYNAMIC)
394#define CH_CFG_USE_DYNAMIC TRUE
395#endif
396
397/** @} */
398
399/*===========================================================================*/
400/**
401 * @name Objects factory options
402 * @{
403 */
404/*===========================================================================*/
405
406/**
407 * @brief Objects Factory APIs.
408 * @details If enabled then the objects factory APIs are included in the
409 * kernel.
410 *
411 * @note The default is @p FALSE.
412 */
413#if !defined(CH_CFG_USE_FACTORY)
414#define CH_CFG_USE_FACTORY TRUE
415#endif
416
417/**
418 * @brief Maximum length for object names.
419 * @details If the specified length is zero then the name is stored by
420 * pointer but this could have unintended side effects.
421 */
422#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
423#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
424#endif
425
426/**
427 * @brief Enables the registry of generic objects.
428 */
429#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
430#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
431#endif
432
433/**
434 * @brief Enables factory for generic buffers.
435 */
436#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
437#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
438#endif
439
440/**
441 * @brief Enables factory for semaphores.
442 */
443#if !defined(CH_CFG_FACTORY_SEMAPHORES)
444#define CH_CFG_FACTORY_SEMAPHORES TRUE
445#endif
446
447/**
448 * @brief Enables factory for mailboxes.
449 */
450#if !defined(CH_CFG_FACTORY_MAILBOXES)
451#define CH_CFG_FACTORY_MAILBOXES TRUE
452#endif
453
454/**
455 * @brief Enables factory for objects FIFOs.
456 */
457#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
458#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
459#endif
460
461/**
462 * @brief Enables factory for Pipes.
463 */
464#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
465#define CH_CFG_FACTORY_PIPES TRUE
466#endif
467
468/** @} */
469
470/*===========================================================================*/
471/**
472 * @name Debug options
473 * @{
474 */
475/*===========================================================================*/
476
477/**
478 * @brief Debug option, kernel statistics.
479 *
480 * @note The default is @p FALSE.
481 */
482#if !defined(CH_DBG_STATISTICS)
483#define CH_DBG_STATISTICS FALSE
484#endif
485
486/**
487 * @brief Debug option, system state check.
488 * @details If enabled the correct call protocol for system APIs is checked
489 * at runtime.
490 *
491 * @note The default is @p FALSE.
492 */
493#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
494#define CH_DBG_SYSTEM_STATE_CHECK FALSE
495#endif
496
497/**
498 * @brief Debug option, parameters checks.
499 * @details If enabled then the checks on the API functions input
500 * parameters are activated.
501 *
502 * @note The default is @p FALSE.
503 */
504#if !defined(CH_DBG_ENABLE_CHECKS)
505#define CH_DBG_ENABLE_CHECKS FALSE
506#endif
507
508/**
509 * @brief Debug option, consistency checks.
510 * @details If enabled then all the assertions in the kernel code are
511 * activated. This includes consistency checks inside the kernel,
512 * runtime anomalies and port-defined checks.
513 *
514 * @note The default is @p FALSE.
515 */
516#if !defined(CH_DBG_ENABLE_ASSERTS)
517#define CH_DBG_ENABLE_ASSERTS FALSE
518#endif
519
520/**
521 * @brief Debug option, trace buffer.
522 * @details If enabled then the trace buffer is activated.
523 *
524 * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
525 */
526#if !defined(CH_DBG_TRACE_MASK)
527#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
528#endif
529
530/**
531 * @brief Trace buffer entries.
532 * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
533 * different from @p CH_DBG_TRACE_MASK_DISABLED.
534 */
535#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
536#define CH_DBG_TRACE_BUFFER_SIZE 128
537#endif
538
539/**
540 * @brief Debug option, stack checks.
541 * @details If enabled then a runtime stack check is performed.
542 *
543 * @note The default is @p FALSE.
544 * @note The stack check is performed in a architecture/port dependent way.
545 * It may not be implemented or some ports.
546 * @note The default failure mode is to halt the system with the global
547 * @p panic_msg variable set to @p NULL.
548 */
549#if !defined(CH_DBG_ENABLE_STACK_CHECK)
550#define CH_DBG_ENABLE_STACK_CHECK TRUE
551#endif
552
553/**
554 * @brief Debug option, stacks initialization.
555 * @details If enabled then the threads working area is filled with a byte
556 * value when a thread is created. This can be useful for the
557 * runtime measurement of the used stack.
558 *
559 * @note The default is @p FALSE.
560 */
561#if !defined(CH_DBG_FILL_THREADS)
562#define CH_DBG_FILL_THREADS FALSE
563#endif
564
565/**
566 * @brief Debug option, threads profiling.
567 * @details If enabled then a field is added to the @p thread_t structure that
568 * counts the system ticks occurred while executing the thread.
569 *
570 * @note The default is @p FALSE.
571 * @note This debug option is not currently compatible with the
572 * tickless mode.
573 */
574#if !defined(CH_DBG_THREADS_PROFILING)
575#define CH_DBG_THREADS_PROFILING FALSE
576#endif
577
578/** @} */
579
580/*===========================================================================*/
581/**
582 * @name Kernel hooks
583 * @{
584 */
585/*===========================================================================*/
586
587/**
588 * @brief System structure extension.
589 * @details User fields added to the end of the @p ch_system_t structure.
590 */
591#define CH_CFG_SYSTEM_EXTRA_FIELDS \
592 /* Add threads custom fields here.*/
593
594/**
595 * @brief System initialization hook.
596 * @details User initialization code added to the @p chSysInit() function
597 * just before interrupts are enabled globally.
598 */
599#define CH_CFG_SYSTEM_INIT_HOOK() { \
600 /* Add threads initialization code here.*/ \
601}
602
603/**
604 * @brief Threads descriptor structure extension.
605 * @details User fields added to the end of the @p thread_t structure.
606 */
607#define CH_CFG_THREAD_EXTRA_FIELDS \
608 /* Add threads custom fields here.*/
609
610/**
611 * @brief Threads initialization hook.
612 * @details User initialization code added to the @p _thread_init() function.
613 *
614 * @note It is invoked from within @p _thread_init() and implicitly from all
615 * the threads creation APIs.
616 */
617#define CH_CFG_THREAD_INIT_HOOK(tp) { \
618 /* Add threads initialization code here.*/ \
619}
620
621/**
622 * @brief Threads finalization hook.
623 * @details User finalization code added to the @p chThdExit() API.
624 */
625#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
626 /* Add threads finalization code here.*/ \
627}
628
629/**
630 * @brief Context switch hook.
631 * @details This hook is invoked just before switching between threads.
632 */
633#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
634 /* Context switch code here.*/ \
635}
636
637/**
638 * @brief ISR enter hook.
639 */
640#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
641 /* IRQ prologue code here.*/ \
642}
643
644/**
645 * @brief ISR exit hook.
646 */
647#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
648 /* IRQ epilogue code here.*/ \
649}
650
651/**
652 * @brief Idle thread enter hook.
653 * @note This hook is invoked within a critical zone, no OS functions
654 * should be invoked from here.
655 * @note This macro can be used to activate a power saving mode.
656 */
657#define CH_CFG_IDLE_ENTER_HOOK() { \
658 /* Idle-enter code here.*/ \
659}
660
661/**
662 * @brief Idle thread leave hook.
663 * @note This hook is invoked within a critical zone, no OS functions
664 * should be invoked from here.
665 * @note This macro can be used to deactivate a power saving mode.
666 */
667#define CH_CFG_IDLE_LEAVE_HOOK() { \
668 /* Idle-leave code here.*/ \
669}
670
671/**
672 * @brief Idle Loop hook.
673 * @details This hook is continuously invoked by the idle thread loop.
674 */
675#define CH_CFG_IDLE_LOOP_HOOK() { \
676 /* Idle loop code here.*/ \
677}
678
679/**
680 * @brief System tick event hook.
681 * @details This hook is invoked in the system tick handler immediately
682 * after processing the virtual timers queue.
683 */
684#define CH_CFG_SYSTEM_TICK_HOOK() { \
685 /* System tick event code here.*/ \
686}
687
688/**
689 * @brief System halt hook.
690 * @details This hook is invoked in case to a system halting error before
691 * the system is halted.
692 */
693#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
694 /* System halt code here.*/ \
695}
696
697/**
698 * @brief Trace hook.
699 * @details This hook is invoked each time a new record is written in the
700 * trace buffer.
701 */
702#define CH_CFG_TRACE_HOOK(tep) { \
703 /* Trace code here.*/ \
704}
705
706/** @} */
707
708/*===========================================================================*/
709/* Port-specific settings (override port settings defaulted in chcore.h). */
710/*===========================================================================*/
711
712#endif /* CHCONF_H */
713
714/** @} */
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h
new file mode 100644
index 000000000..6b48e289f
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h
@@ -0,0 +1,525 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file templates/halconf.h
19 * @brief HAL configuration header.
20 * @details HAL configuration file, this file allows to enable or disable the
21 * various device drivers from your application. You may also use
22 * this file in order to override the device drivers default settings.
23 *
24 * @addtogroup HAL_CONF
25 * @{
26 */
27
28#ifndef HALCONF_H
29#define HALCONF_H
30
31#define _CHIBIOS_HAL_CONF_
32#define _CHIBIOS_HAL_CONF_VER_7_0_
33
34#include "mcuconf.h"
35
36/**
37 * @brief Enables the PAL subsystem.
38 */
39#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
40#define HAL_USE_PAL TRUE
41#endif
42
43/**
44 * @brief Enables the ADC subsystem.
45 */
46#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
47#define HAL_USE_ADC FALSE
48#endif
49
50/**
51 * @brief Enables the CAN subsystem.
52 */
53#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
54#define HAL_USE_CAN FALSE
55#endif
56
57/**
58 * @brief Enables the cryptographic subsystem.
59 */
60#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
61#define HAL_USE_CRY FALSE
62#endif
63
64/**
65 * @brief Enables the DAC subsystem.
66 */
67#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
68#define HAL_USE_DAC TRUE
69#endif
70
71/**
72 * @brief Enables the GPT subsystem.
73 */
74#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
75#define HAL_USE_GPT TRUE
76#endif
77
78/**
79 * @brief Enables the I2C subsystem.
80 */
81#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
82#define HAL_USE_I2C TRUE
83#endif
84
85/**
86 * @brief Enables the I2S subsystem.
87 */
88#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
89#define HAL_USE_I2S FALSE
90#endif
91
92/**
93 * @brief Enables the ICU subsystem.
94 */
95#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
96#define HAL_USE_ICU FALSE
97#endif
98
99/**
100 * @brief Enables the MAC subsystem.
101 */
102#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
103#define HAL_USE_MAC FALSE
104#endif
105
106/**
107 * @brief Enables the MMC_SPI subsystem.
108 */
109#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
110#define HAL_USE_MMC_SPI FALSE
111#endif
112
113/**
114 * @brief Enables the PWM subsystem.
115 */
116#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
117#define HAL_USE_PWM TRUE
118#endif
119
120/**
121 * @brief Enables the RTC subsystem.
122 */
123#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
124#define HAL_USE_RTC FALSE
125#endif
126
127/**
128 * @brief Enables the SDC subsystem.
129 */
130#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
131#define HAL_USE_SDC FALSE
132#endif
133
134/**
135 * @brief Enables the SERIAL subsystem.
136 */
137#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
138#define HAL_USE_SERIAL FALSE
139#endif
140
141/**
142 * @brief Enables the SERIAL over USB subsystem.
143 */
144#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
145#define HAL_USE_SERIAL_USB TRUE
146#endif
147
148/**
149 * @brief Enables the SIO subsystem.
150 */
151#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
152#define HAL_USE_SIO FALSE
153#endif
154
155/**
156 * @brief Enables the SPI subsystem.
157 */
158#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
159#define HAL_USE_SPI TRUE
160#endif
161
162/**
163 * @brief Enables the TRNG subsystem.
164 */
165#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
166#define HAL_USE_TRNG FALSE
167#endif
168
169/**
170 * @brief Enables the UART subsystem.
171 */
172#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
173#define HAL_USE_UART FALSE
174#endif
175
176/**
177 * @brief Enables the USB subsystem.
178 */
179#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
180#define HAL_USE_USB TRUE
181#endif
182
183/**
184 * @brief Enables the WDG subsystem.
185 */
186#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
187#define HAL_USE_WDG FALSE
188#endif
189
190/**
191 * @brief Enables the WSPI subsystem.
192 */
193#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
194#define HAL_USE_WSPI FALSE
195#endif
196
197/*===========================================================================*/
198/* PAL driver related settings. */
199/*===========================================================================*/
200
201/**
202 * @brief Enables synchronous APIs.
203 * @note Disabling this option saves both code and data space.
204 */
205#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
206#define PAL_USE_CALLBACKS TRUE
207#endif
208
209/**
210 * @brief Enables synchronous APIs.
211 * @note Disabling this option saves both code and data space.
212 */
213#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
214#define PAL_USE_WAIT TRUE
215#endif
216
217/*===========================================================================*/
218/* ADC driver related settings. */
219/*===========================================================================*/
220
221/**
222 * @brief Enables synchronous APIs.
223 * @note Disabling this option saves both code and data space.
224 */
225#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
226#define ADC_USE_WAIT TRUE
227#endif
228
229/**
230 * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
231 * @note Disabling this option saves both code and data space.
232 */
233#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
234#define ADC_USE_MUTUAL_EXCLUSION TRUE
235#endif
236
237/*===========================================================================*/
238/* CAN driver related settings. */
239/*===========================================================================*/
240
241/**
242 * @brief Sleep mode related APIs inclusion switch.
243 */
244#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
245#define CAN_USE_SLEEP_MODE TRUE
246#endif
247
248/**
249 * @brief Enforces the driver to use direct callbacks rather than OSAL events.
250 */
251#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
252#define CAN_ENFORCE_USE_CALLBACKS FALSE
253#endif
254
255/*===========================================================================*/
256/* CRY driver related settings. */
257/*===========================================================================*/
258
259/**
260 * @brief Enables the SW fall-back of the cryptographic driver.
261 * @details When enabled, this option, activates a fall-back software
262 * implementation for algorithms not supported by the underlying
263 * hardware.
264 * @note Fall-back implementations may not be present for all algorithms.
265 */
266#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
267#define HAL_CRY_USE_FALLBACK FALSE
268#endif
269
270/**
271 * @brief Makes the driver forcibly use the fall-back implementations.
272 */
273#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
274#define HAL_CRY_ENFORCE_FALLBACK FALSE
275#endif
276
277/*===========================================================================*/
278/* DAC driver related settings. */
279/*===========================================================================*/
280
281/**
282 * @brief Enables synchronous APIs.
283 * @note Disabling this option saves both code and data space.
284 */
285#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
286#define DAC_USE_WAIT TRUE
287#endif
288
289/**
290 * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
291 * @note Disabling this option saves both code and data space.
292 */
293#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
294#define DAC_USE_MUTUAL_EXCLUSION TRUE
295#endif
296
297/*===========================================================================*/
298/* I2C driver related settings. */
299/*===========================================================================*/
300
301/**
302 * @brief Enables the mutual exclusion APIs on the I2C bus.
303 */
304#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
305#define I2C_USE_MUTUAL_EXCLUSION TRUE
306#endif
307
308/*===========================================================================*/
309/* MAC driver related settings. */
310/*===========================================================================*/
311
312/**
313 * @brief Enables the zero-copy API.
314 */
315#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
316#define MAC_USE_ZERO_COPY FALSE
317#endif
318
319/**
320 * @brief Enables an event sources for incoming packets.
321 */
322#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
323#define MAC_USE_EVENTS TRUE
324#endif
325
326/*===========================================================================*/
327/* MMC_SPI driver related settings. */
328/*===========================================================================*/
329
330/**
331 * @brief Delays insertions.
332 * @details If enabled this options inserts delays into the MMC waiting
333 * routines releasing some extra CPU time for the threads with
334 * lower priority, this may slow down the driver a bit however.
335 * This option is recommended also if the SPI driver does not
336 * use a DMA channel and heavily loads the CPU.
337 */
338#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
339#define MMC_NICE_WAITING TRUE
340#endif
341
342/*===========================================================================*/
343/* SDC driver related settings. */
344/*===========================================================================*/
345
346/**
347 * @brief Number of initialization attempts before rejecting the card.
348 * @note Attempts are performed at 10mS intervals.
349 */
350#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
351#define SDC_INIT_RETRY 100
352#endif
353
354/**
355 * @brief Include support for MMC cards.
356 * @note MMC support is not yet implemented so this option must be kept
357 * at @p FALSE.
358 */
359#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
360#define SDC_MMC_SUPPORT FALSE
361#endif
362
363/**
364 * @brief Delays insertions.
365 * @details If enabled this options inserts delays into the MMC waiting
366 * routines releasing some extra CPU time for the threads with
367 * lower priority, this may slow down the driver a bit however.
368 */
369#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
370#define SDC_NICE_WAITING TRUE
371#endif
372
373/**
374 * @brief OCR initialization constant for V20 cards.
375 */
376#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
377#define SDC_INIT_OCR_V20 0x50FF8000U
378#endif
379
380/**
381 * @brief OCR initialization constant for non-V20 cards.
382 */
383#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
384#define SDC_INIT_OCR 0x80100000U
385#endif
386
387/*===========================================================================*/
388/* SERIAL driver related settings. */
389/*===========================================================================*/
390
391/**
392 * @brief Default bit rate.
393 * @details Configuration parameter, this is the baud rate selected for the
394 * default configuration.
395 */
396#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
397#define SERIAL_DEFAULT_BITRATE 38400
398#endif
399
400/**
401 * @brief Serial buffers size.
402 * @details Configuration parameter, you can change the depth of the queue
403 * buffers depending on the requirements of your application.
404 * @note The default is 16 bytes for both the transmission and receive
405 * buffers.
406 */
407#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
408#define SERIAL_BUFFERS_SIZE 16
409#endif
410
411/*===========================================================================*/
412/* SERIAL_USB driver related setting. */
413/*===========================================================================*/
414
415/**
416 * @brief Serial over USB buffers size.
417 * @details Configuration parameter, the buffer size must be a multiple of
418 * the USB data endpoint maximum packet size.
419 * @note The default is 256 bytes for both the transmission and receive
420 * buffers.
421 */
422#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
423#define SERIAL_USB_BUFFERS_SIZE 1
424#endif
425
426/**
427 * @brief Serial over USB number of buffers.
428 * @note The default is 2 buffers.
429 */
430#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
431#define SERIAL_USB_BUFFERS_NUMBER 2
432#endif
433
434/*===========================================================================*/
435/* SPI driver related settings. */
436/*===========================================================================*/
437
438/**
439 * @brief Enables synchronous APIs.
440 * @note Disabling this option saves both code and data space.
441 */
442#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
443#define SPI_USE_WAIT TRUE
444#endif
445
446/**
447 * @brief Enables circular transfers APIs.
448 * @note Disabling this option saves both code and data space.
449 */
450#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
451#define SPI_USE_CIRCULAR FALSE
452#endif
453
454
455/**
456 * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
457 * @note Disabling this option saves both code and data space.
458 */
459#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
460#define SPI_USE_MUTUAL_EXCLUSION TRUE
461#endif
462
463/**
464 * @brief Handling method for SPI CS line.
465 * @note Disabling this option saves both code and data space.
466 */
467#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
468#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
469#endif
470
471/*===========================================================================*/
472/* UART driver related settings. */
473/*===========================================================================*/
474
475/**
476 * @brief Enables synchronous APIs.
477 * @note Disabling this option saves both code and data space.
478 */
479#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
480#define UART_USE_WAIT FALSE
481#endif
482
483/**
484 * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
485 * @note Disabling this option saves both code and data space.
486 */
487#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
488#define UART_USE_MUTUAL_EXCLUSION FALSE
489#endif
490
491/*===========================================================================*/
492/* USB driver related settings. */
493/*===========================================================================*/
494
495/**
496 * @brief Enables synchronous APIs.
497 * @note Disabling this option saves both code and data space.
498 */
499#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
500#define USB_USE_WAIT TRUE
501#endif
502
503/*===========================================================================*/
504/* WSPI driver related settings. */
505/*===========================================================================*/
506
507/**
508 * @brief Enables synchronous APIs.
509 * @note Disabling this option saves both code and data space.
510 */
511#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
512#define WSPI_USE_WAIT TRUE
513#endif
514
515/**
516 * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
517 * @note Disabling this option saves both code and data space.
518 */
519#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
520#define WSPI_USE_MUTUAL_EXCLUSION TRUE
521#endif
522
523#endif /* HALCONF_H */
524
525/** @} */
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h
new file mode 100644
index 000000000..3b1588348
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h
@@ -0,0 +1,273 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#ifndef MCUCONF_H
18#define MCUCONF_H
19
20/*
21 * STM32F3xx drivers configuration.
22 * The following settings override the default settings present in
23 * the various device driver implementation headers.
24 * Note that the settings for each driver only have effect if the whole
25 * driver is enabled in halconf.h.
26 *
27 * IRQ priorities:
28 * 15...0 Lowest...Highest.
29 *
30 * DMA priorities:
31 * 0...3 Lowest...Highest.
32 */
33
34#define STM32F3xx_MCUCONF
35#define STM32F303_MCUCONF
36
37/*
38 * HAL driver system settings.
39 */
40#define STM32_NO_INIT FALSE
41#define STM32_PVD_ENABLE FALSE
42#define STM32_PLS STM32_PLS_LEV0
43#define STM32_HSI_ENABLED TRUE
44#define STM32_LSI_ENABLED TRUE
45#define STM32_HSE_ENABLED TRUE
46#define STM32_LSE_ENABLED FALSE
47#define STM32_SW STM32_SW_PLL
48#define STM32_PLLSRC STM32_PLLSRC_HSE
49#define STM32_PREDIV_VALUE 1
50#define STM32_PLLMUL_VALUE 9
51#define STM32_HPRE STM32_HPRE_DIV1
52#define STM32_PPRE1 STM32_PPRE1_DIV2
53#define STM32_PPRE2 STM32_PPRE2_DIV2
54#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
55#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
56#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
57#define STM32_USART1SW STM32_USART1SW_PCLK
58#define STM32_USART2SW STM32_USART2SW_PCLK
59#define STM32_USART3SW STM32_USART3SW_PCLK
60#define STM32_UART4SW STM32_UART4SW_PCLK
61#define STM32_UART5SW STM32_UART5SW_PCLK
62#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
63#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
64#define STM32_TIM1SW STM32_TIM1SW_PCLK2
65#define STM32_TIM8SW STM32_TIM8SW_PCLK2
66#define STM32_RTCSEL STM32_RTCSEL_LSI
67#define STM32_USB_CLOCK_REQUIRED TRUE
68#define STM32_USBPRE STM32_USBPRE_DIV1P5
69
70/*
71 * IRQ system settings.
72 */
73#define STM32_IRQ_EXTI0_PRIORITY 6
74#define STM32_IRQ_EXTI1_PRIORITY 6
75#define STM32_IRQ_EXTI2_PRIORITY 6
76#define STM32_IRQ_EXTI3_PRIORITY 6
77#define STM32_IRQ_EXTI4_PRIORITY 6
78#define STM32_IRQ_EXTI5_9_PRIORITY 6
79#define STM32_IRQ_EXTI10_15_PRIORITY 6
80#define STM32_IRQ_EXTI16_PRIORITY 6
81#define STM32_IRQ_EXTI17_PRIORITY 15
82#define STM32_IRQ_EXTI18_PRIORITY 6
83#define STM32_IRQ_EXTI19_PRIORITY 15
84#define STM32_IRQ_EXTI20_PRIORITY 15
85#define STM32_IRQ_EXTI21_22_29_PRIORITY 6
86#define STM32_IRQ_EXTI30_32_PRIORITY 6
87#define STM32_IRQ_EXTI33_PRIORITY 6
88#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
89#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
90#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
91#define STM32_IRQ_TIM1_CC_PRIORITY 7
92
93/*
94 * ADC driver system settings.
95 */
96#define STM32_ADC_DUAL_MODE FALSE
97#define STM32_ADC_COMPACT_SAMPLES FALSE
98#define STM32_ADC_USE_ADC1 FALSE
99#define STM32_ADC_USE_ADC2 FALSE
100#define STM32_ADC_USE_ADC3 FALSE
101#define STM32_ADC_USE_ADC4 FALSE
102#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
103#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
104#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
105#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
106#define STM32_ADC_ADC1_DMA_PRIORITY 2
107#define STM32_ADC_ADC2_DMA_PRIORITY 2
108#define STM32_ADC_ADC3_DMA_PRIORITY 2
109#define STM32_ADC_ADC4_DMA_PRIORITY 2
110#define STM32_ADC_ADC12_IRQ_PRIORITY 5
111#define STM32_ADC_ADC3_IRQ_PRIORITY 5
112#define STM32_ADC_ADC4_IRQ_PRIORITY 5
113#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
114#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
115#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
116#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
117#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
118#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
119
120/*
121 * CAN driver system settings.
122 */
123#define STM32_CAN_USE_CAN1 FALSE
124#define STM32_CAN_CAN1_IRQ_PRIORITY 11
125
126/*
127 * DAC driver system settings.
128 */
129#define STM32_DAC_DUAL_MODE FALSE
130#define STM32_DAC_USE_DAC1_CH1 TRUE
131#define STM32_DAC_USE_DAC1_CH2 TRUE
132#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
133#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
134#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
135#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
136
137/*
138 * GPT driver system settings.
139 */
140#define STM32_GPT_USE_TIM1 FALSE
141#define STM32_GPT_USE_TIM2 FALSE
142#define STM32_GPT_USE_TIM3 FALSE
143#define STM32_GPT_USE_TIM4 FALSE
144#define STM32_GPT_USE_TIM6 TRUE
145#define STM32_GPT_USE_TIM7 TRUE
146#define STM32_GPT_USE_TIM8 TRUE
147#define STM32_GPT_USE_TIM15 FALSE
148#define STM32_GPT_USE_TIM16 FALSE
149#define STM32_GPT_USE_TIM17 FALSE
150#define STM32_GPT_TIM1_IRQ_PRIORITY 7
151#define STM32_GPT_TIM2_IRQ_PRIORITY 7
152#define STM32_GPT_TIM3_IRQ_PRIORITY 7
153#define STM32_GPT_TIM4_IRQ_PRIORITY 7
154#define STM32_GPT_TIM6_IRQ_PRIORITY 7
155#define STM32_GPT_TIM7_IRQ_PRIORITY 7
156#define STM32_GPT_TIM8_IRQ_PRIORITY 7
157
158/*
159 * I2C driver system settings.
160 */
161#define STM32_I2C_USE_I2C1 TRUE
162#define STM32_I2C_USE_I2C2 FALSE
163#define STM32_I2C_BUSY_TIMEOUT 50
164#define STM32_I2C_I2C1_IRQ_PRIORITY 10
165#define STM32_I2C_I2C2_IRQ_PRIORITY 10
166#define STM32_I2C_USE_DMA TRUE
167#define STM32_I2C_I2C1_DMA_PRIORITY 1
168#define STM32_I2C_I2C2_DMA_PRIORITY 1
169#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
170
171/*
172 * ICU driver system settings.
173 */
174#define STM32_ICU_USE_TIM1 FALSE
175#define STM32_ICU_USE_TIM2 FALSE
176#define STM32_ICU_USE_TIM3 FALSE
177#define STM32_ICU_USE_TIM4 FALSE
178#define STM32_ICU_USE_TIM8 FALSE
179#define STM32_ICU_USE_TIM15 FALSE
180#define STM32_ICU_TIM1_IRQ_PRIORITY 7
181#define STM32_ICU_TIM2_IRQ_PRIORITY 7
182#define STM32_ICU_TIM3_IRQ_PRIORITY 7
183#define STM32_ICU_TIM4_IRQ_PRIORITY 7
184#define STM32_ICU_TIM8_IRQ_PRIORITY 7
185
186/*
187 * PWM driver system settings.
188 */
189#define STM32_PWM_USE_ADVANCED FALSE
190#define STM32_PWM_USE_TIM1 FALSE
191#define STM32_PWM_USE_TIM2 FALSE
192#define STM32_PWM_USE_TIM3 TRUE
193#define STM32_PWM_USE_TIM4 TRUE
194#define STM32_PWM_USE_TIM8 FALSE
195#define STM32_PWM_USE_TIM15 FALSE
196#define STM32_PWM_USE_TIM16 FALSE
197#define STM32_PWM_USE_TIM17 FALSE
198#define STM32_PWM_TIM1_IRQ_PRIORITY 7
199#define STM32_PWM_TIM2_IRQ_PRIORITY 7
200#define STM32_PWM_TIM3_IRQ_PRIORITY 7
201#define STM32_PWM_TIM4_IRQ_PRIORITY 7
202#define STM32_PWM_TIM8_IRQ_PRIORITY 7
203
204/*
205 * RTC driver system settings.
206 */
207#define STM32_RTC_PRESA_VALUE 32
208#define STM32_RTC_PRESS_VALUE 1024
209#define STM32_RTC_CR_INIT 0
210#define STM32_RTC_TAMPCR_INIT 0
211
212/*
213 * SERIAL driver system settings.
214 */
215#define STM32_SERIAL_USE_USART1 FALSE
216#define STM32_SERIAL_USE_USART2 TRUE
217#define STM32_SERIAL_USE_USART3 FALSE
218#define STM32_SERIAL_USE_UART4 FALSE
219#define STM32_SERIAL_USE_UART5 FALSE
220#define STM32_SERIAL_USART1_PRIORITY 12
221#define STM32_SERIAL_USART2_PRIORITY 12
222#define STM32_SERIAL_USART3_PRIORITY 12
223#define STM32_SERIAL_UART4_PRIORITY 12
224#define STM32_SERIAL_UART5_PRIORITY 12
225
226/*
227 * SPI driver system settings.
228 */
229#define STM32_SPI_USE_SPI1 FALSE
230#define STM32_SPI_USE_SPI2 TRUE
231#define STM32_SPI_USE_SPI3 FALSE
232#define STM32_SPI_SPI1_DMA_PRIORITY 1
233#define STM32_SPI_SPI2_DMA_PRIORITY 1
234#define STM32_SPI_SPI3_DMA_PRIORITY 1
235#define STM32_SPI_SPI1_IRQ_PRIORITY 10
236#define STM32_SPI_SPI2_IRQ_PRIORITY 10
237#define STM32_SPI_SPI3_IRQ_PRIORITY 10
238#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
239
240/*
241 * ST driver system settings.
242 */
243#define STM32_ST_IRQ_PRIORITY 8
244#define STM32_ST_USE_TIMER 2
245
246/*
247 * UART driver system settings.
248 */
249#define STM32_UART_USE_USART1 FALSE
250#define STM32_UART_USE_USART2 FALSE
251#define STM32_UART_USE_USART3 FALSE
252#define STM32_UART_USART1_IRQ_PRIORITY 12
253#define STM32_UART_USART2_IRQ_PRIORITY 12
254#define STM32_UART_USART3_IRQ_PRIORITY 12
255#define STM32_UART_USART1_DMA_PRIORITY 0
256#define STM32_UART_USART2_DMA_PRIORITY 0
257#define STM32_UART_USART3_DMA_PRIORITY 0
258#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
259
260/*
261 * USB driver system settings.
262 */
263#define STM32_USB_USE_USB1 TRUE
264#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
265#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
266#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
267
268/*
269 * WDG driver system settings.
270 */
271#define STM32_WDG_USE_IWDG FALSE
272
273#endif /* MCUCONF_H */
diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk b/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk
new file mode 100644
index 000000000..23907c810
--- /dev/null
+++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk
@@ -0,0 +1,9 @@
1# Proton C MCU settings for converting AVR projects
2MCU = STM32F303
3
4# These are defaults based on what has been implemented for ARM boards
5AUDIO_ENABLE = yes
6WS2812_DRIVER = bitbang
7
8# Force task driven PWM until ARM can provide automatic configuration
9BACKLIGHT_DRIVER = software
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 05:17:38 +0000